source: trunk/FirmwareFX2/fx2/syncdelay.h@ 197

Last change on this file since 197 was 4, checked in by demin, 15 years ago

initial commit

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1/* -*- c++ -*- */
2/*-----------------------------------------------------------------------------
3 * Synchronization delay for FX2 access to specific registers
4 *-----------------------------------------------------------------------------
5 * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
6 * Copyright 2003 Free Software Foundation, Inc.
7 *-----------------------------------------------------------------------------
8 * This code is part of usbjtag. usbjtag is free software; you can redistribute
9 * it and/or modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the License,
11 * or (at your option) any later version. usbjtag is distributed in the hope
12 * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
13 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. You should have received a
15 * copy of the GNU General Public License along with this program in the file
16 * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
17 * St, Fifth Floor, Boston, MA 02110-1301 USA
18 *-----------------------------------------------------------------------------
19 */
20
21#ifndef _SYNCDELAY_H_
22#define _SYNCDELAY_H_
23
24/*
25 * Magic delay required between access to certain xdata registers (TRM page 15-106).
26 * For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
27 * NOP is a single cycle....
28 *
29 * From TRM page 15-105:
30 *
31 * Under certain conditions, some read and write access to the FX2 registers must
32 * be separated by a "synchronization delay". The delay is necessary only under the
33 * following conditions:
34 *
35 * - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
36 * of the registers listed below.
37 *
38 * - between a write to one of the registers listed below and a read from any register
39 * in the 0xE600 - 0xE6FF range.
40 *
41 * Registers which require a synchronization delay:
42 *
43 * FIFORESET FIFOPINPOLAR
44 * INPKTEND EPxBCH:L
45 * EPxFIFOPFH:L EPxAUTOINLENH:L
46 * EPxFIFOCFG EPxGPIFFLGSEL
47 * PINFLAGSAB PINFLAGSCD
48 * EPxFIFOIE EPxFIFOIRQ
49 * GPIFIE GPIFIRQ
50 * UDMACRCH:L GPIFADRH:L
51 * GPIFTRIG EPxGPIFTRIG
52 * OUTPKTEND REVCTL
53 * GPIFTCB3 GPIFTCB2
54 * GPIFTCB1 GPIFTCB0
55 */
56
57/*
58 * FIXME ensure that the peep hole optimizer isn't screwing us
59 */
60#define SYNCDELAY _asm nop; nop; nop; _endasm
61#define NOP _asm nop; _endasm
62
63
64#endif /* _SYNCDELAY_H_ */
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