| 1 | /* -*- c++ -*- */
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| 2 | /*-----------------------------------------------------------------------------
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| 3 | * Synchronization delay for FX2 access to specific registers
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| 4 | *-----------------------------------------------------------------------------
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| 5 | * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
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| 6 | * Copyright 2003 Free Software Foundation, Inc.
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| 7 | *-----------------------------------------------------------------------------
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| 8 | * This code is part of usbjtag. usbjtag is free software; you can redistribute
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| 9 | * it and/or modify it under the terms of the GNU General Public License as
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| 10 | * published by the Free Software Foundation; either version 2 of the License,
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| 11 | * or (at your option) any later version. usbjtag is distributed in the hope
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| 12 | * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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| 13 | * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 14 | * GNU General Public License for more details. You should have received a
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| 15 | * copy of the GNU General Public License along with this program in the file
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| 16 | * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
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| 17 | * St, Fifth Floor, Boston, MA 02110-1301 USA
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| 18 | *-----------------------------------------------------------------------------
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| 19 | */
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| 20 |
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| 21 | #ifndef _SYNCDELAY_H_
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| 22 | #define _SYNCDELAY_H_
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| 23 |
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| 24 | /*
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| 25 | * Magic delay required between access to certain xdata registers (TRM page 15-106).
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| 26 | * For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
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| 27 | * NOP is a single cycle....
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| 28 | *
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| 29 | * From TRM page 15-105:
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| 30 | *
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| 31 | * Under certain conditions, some read and write access to the FX2 registers must
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| 32 | * be separated by a "synchronization delay". The delay is necessary only under the
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| 33 | * following conditions:
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| 34 | *
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| 35 | * - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
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| 36 | * of the registers listed below.
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| 37 | *
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| 38 | * - between a write to one of the registers listed below and a read from any register
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| 39 | * in the 0xE600 - 0xE6FF range.
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| 40 | *
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| 41 | * Registers which require a synchronization delay:
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| 42 | *
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| 43 | * FIFORESET FIFOPINPOLAR
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| 44 | * INPKTEND EPxBCH:L
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| 45 | * EPxFIFOPFH:L EPxAUTOINLENH:L
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| 46 | * EPxFIFOCFG EPxGPIFFLGSEL
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| 47 | * PINFLAGSAB PINFLAGSCD
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| 48 | * EPxFIFOIE EPxFIFOIRQ
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| 49 | * GPIFIE GPIFIRQ
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| 50 | * UDMACRCH:L GPIFADRH:L
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| 51 | * GPIFTRIG EPxGPIFTRIG
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| 52 | * OUTPKTEND REVCTL
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| 53 | * GPIFTCB3 GPIFTCB2
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| 54 | * GPIFTCB1 GPIFTCB0
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| 55 | */
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| 56 |
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| 57 | /*
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| 58 | * FIXME ensure that the peep hole optimizer isn't screwing us
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| 59 | */
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| 60 | #define SYNCDELAY _asm nop; nop; nop; _endasm
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| 61 | #define NOP _asm nop; _endasm
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| 62 |
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| 63 |
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| 64 | #endif /* _SYNCDELAY_H_ */
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