| [4] | 1 | /* -*- c++ -*- */
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| 2 | /*-----------------------------------------------------------------------------
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| 3 | * FX2 register definitions
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| 4 | *-----------------------------------------------------------------------------
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| 5 | * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
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| 6 | * Copyright 2003 Free Software Foundation, Inc.
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| 7 | *-----------------------------------------------------------------------------
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| 8 | * This code is part of usbjtag. usbjtag is free software; you can redistribute
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| 9 | * it and/or modify it under the terms of the GNU General Public License as
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| 10 | * published by the Free Software Foundation; either version 2 of the License,
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| 11 | * or (at your option) any later version. usbjtag is distributed in the hope
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| 12 | * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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| 13 | * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 14 | * GNU General Public License for more details. You should have received a
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| 15 | * copy of the GNU General Public License along with this program in the file
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| 16 | * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
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| 17 | * St, Fifth Floor, Boston, MA 02110-1301 USA
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| 18 | *-----------------------------------------------------------------------------
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| 19 | */
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| 20 |
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| 21 | /*
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| 22 | //-----------------------------------------------------------------------------
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| 23 | // File: FX2regs.h
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| 24 | // Contents: EZ-USB FX2 register declarations and bit mask definitions.
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| 25 | //
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| 26 | // $Archive: /USB/Target/Inc/fx2regs.h $
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| 27 | // $Date: 2009-08-26 09:14:41 $
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| 28 | // $Revision: 1.1 $
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| 29 | //
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| 30 | //
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| 31 | // Copyright (c) 2000 Cypress Semiconductor, All rights reserved
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| 32 | //-----------------------------------------------------------------------------
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| 33 | */
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| 34 |
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| 35 |
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| 36 | #ifndef FX2REGS_H /* Header Sentry */
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| 37 | #define FX2REGS_H
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| 38 |
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| 39 | #define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h
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| 40 |
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| 41 | /*
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| 42 | //-----------------------------------------------------------------------------
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| 43 | // FX2 Related Register Assignments
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| 44 | //-----------------------------------------------------------------------------
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| 45 |
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| 46 | // The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
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| 47 | // address allocation by using "#define ALLOCATE_EXTERN".
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| 48 | // When using "#define ALLOCATE_EXTERN", you get (for instance):
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| 49 | // xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
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| 50 | // Such lines are created from FX2.h by using the preprocessor.
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| 51 | // Incidently, these lines will not generate any space in the resulting hex
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| 52 | // file; they just bind the symbols to the addresses for compilation.
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| 53 | // You just need to put "#define ALLOCATE_EXTERN" in your main program file;
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| 54 | // i.e. fw.c or a stand-alone C source file.
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| 55 | // Without "#define ALLOCATE_EXTERN", you just get the external reference:
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| 56 | // extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
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| 57 | // This uses the concatenation operator "##" to insert a comment "//"
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| 58 | // to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
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| 59 | */
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| 60 |
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| 61 |
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| 62 | #ifdef ALLOCATE_EXTERN
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| 63 | #define EXTERN
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| 64 | #define _AT_(a) at a
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| 65 | #else
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| 66 | #define EXTERN extern
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| 67 | #define _AT_ ;/ ## /
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| 68 | #endif
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| 69 |
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| 70 | typedef unsigned char BYTE;
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| 71 | typedef unsigned short WORD;
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| 72 |
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| 73 | EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];
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| 74 | EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
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| 75 |
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| 76 | // General Configuration
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| 77 |
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| 78 | EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
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| 79 | EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
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| 80 | EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
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| 81 | EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
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| 82 | EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
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| 83 | EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
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| 84 | EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
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| 85 | EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
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| 86 | EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
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| 87 | EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
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| 88 | EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
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| 89 | EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
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| 90 |
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| 91 | // Endpoint Configuration
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| 92 |
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| 93 | EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
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| 94 | EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
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| 95 | EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
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| 96 | EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
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| 97 | EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
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| 98 | EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
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| 99 | EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
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| 100 | EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
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| 101 | EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
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| 102 | EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
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| 103 | EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
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| 104 | EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
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| 105 | EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
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| 106 | EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
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| 107 | EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
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| 108 | EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
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| 109 | EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
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| 110 | EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
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| 111 | EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
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| 112 | EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
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| 113 | EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
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| 114 | EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
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| 115 | EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
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| 116 | EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
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| 117 | EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
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| 118 | EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
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| 119 | EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
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| 120 | EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
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| 121 | EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
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| 122 | EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
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| 123 | EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
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| 124 | EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
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| 125 |
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| 126 | // Interrupts
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| 127 |
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| 128 | EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
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| 129 | EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
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| 130 | EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
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| 131 | EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
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| 132 | EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
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| 133 | EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
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| 134 | EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
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| 135 | EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
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| 136 | EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
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| 137 | EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
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| 138 | EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
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| 139 | EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
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| 140 | EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
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| 141 | EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
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| 142 | EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
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| 143 | EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
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| 144 | EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
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| 145 | EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
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| 146 | EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
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| 147 | EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
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| 148 | EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
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| 149 | EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
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| 150 | EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
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| 151 | EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
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| 152 | EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
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| 153 |
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| 154 | // Input/Output
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| 155 |
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| 156 | EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
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| 157 | EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
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| 158 | EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
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| 159 | EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
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| 160 | EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
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| 161 | EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
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| 162 | EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
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| 163 | EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
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| 164 |
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| 165 | #define EXTAUTODAT1 XAUTODAT1
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| 166 | #define EXTAUTODAT2 XAUTODAT2
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| 167 |
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| 168 | // USB Control
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| 169 |
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| 170 | EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
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| 171 | EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
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| 172 | EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
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| 173 | EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
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| 174 | EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
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| 175 | EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
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| 176 | EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
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| 177 | EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
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| 178 |
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| 179 | // Endpoints
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| 180 |
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| 181 | EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
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| 182 | EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
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| 183 | EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
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| 184 | EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
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| 185 | EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
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| 186 | EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
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| 187 | EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
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| 188 | EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
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| 189 | EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
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| 190 | EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
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| 191 | EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
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| 192 | EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
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| 193 | EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
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| 194 | EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
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| 195 | EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
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| 196 | EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
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| 197 | EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
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| 198 | EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
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| 199 | EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
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| 200 | EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
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| 201 | EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
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| 202 | EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
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| 203 | EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
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| 204 | EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
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| 205 | EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
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| 206 | EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
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| 207 | EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
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| 208 | EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
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| 209 | EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
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| 210 | EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
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| 211 | EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
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| 212 | EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
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| 213 | EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
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| 214 | EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
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| 215 | EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
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| 216 |
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| 217 | // GPIF
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| 218 |
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| 219 | EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
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| 220 | EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
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| 221 | EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
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| 222 | EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
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| 223 | EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
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| 224 | EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
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| 225 |
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| 226 | EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
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| 227 | EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
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| 228 | EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
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| 229 | EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
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| 230 |
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| 231 | #define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
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| 232 | #define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
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| 233 | #define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility
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| 234 | #define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
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| 235 | #define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility
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| 236 | #define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
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| 237 | #define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
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| 238 | #define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
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| 239 |
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| 240 | // EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
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| 241 | // EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
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| 242 | EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
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| 243 | EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
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| 244 | EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
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| 245 | // EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
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| 246 | // EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
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| 247 | EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
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| 248 | EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
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| 249 | EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
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| 250 | // EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
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| 251 | // EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
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| 252 | EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
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| 253 | EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
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| 254 | EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
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| 255 | // EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
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| 256 | // EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
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| 257 | EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
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| 258 | EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
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| 259 | EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
|
|---|
| 260 | EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
|
|---|
| 261 | EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
|
|---|
| 262 | EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
|
|---|
| 263 | EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
|
|---|
| 264 | EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
|
|---|
| 265 | EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
|
|---|
| 266 |
|
|---|
| 267 | // UDMA
|
|---|
| 268 |
|
|---|
| 269 | EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
|
|---|
| 270 | EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
|
|---|
| 271 | EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
|
|---|
| 272 | EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
|
|---|
| 273 | EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
|
|---|
| 274 | EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
|
|---|
| 275 | EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
|
|---|
| 276 | EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
|
|---|
| 277 | EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
|
|---|
| 278 | EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
|
|---|
| 279 | EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
|
|---|
| 280 | EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
|
|---|
| 281 |
|
|---|
| 282 |
|
|---|
| 283 | // Debug/Test
|
|---|
| 284 |
|
|---|
| 285 | EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
|
|---|
| 286 | EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
|
|---|
| 287 | EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
|
|---|
| 288 | EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
|
|---|
| 289 | EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
|
|---|
| 290 | EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
|
|---|
| 291 | EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
|
|---|
| 292 |
|
|---|
| 293 | // Endpoint Buffers
|
|---|
| 294 |
|
|---|
| 295 | EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
|
|---|
| 296 | EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
|
|---|
| 297 | EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
|
|---|
| 298 | EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
|
|---|
| 299 | EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
|
|---|
| 300 | EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
|
|---|
| 301 | EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
|
|---|
| 302 |
|
|---|
| 303 | #undef EXTERN
|
|---|
| 304 | #undef _AT_
|
|---|
| 305 |
|
|---|
| 306 | /*-----------------------------------------------------------------------------
|
|---|
| 307 | Special Function Registers (SFRs)
|
|---|
| 308 | The byte registers and bits defined in the following list are based
|
|---|
| 309 | on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
|
|---|
| 310 | If you modify the register definitions below, please regenerate the file
|
|---|
| 311 | "ezregs.inc" which includes the same basic information for assembly inclusion.
|
|---|
| 312 | -----------------------------------------------------------------------------*/
|
|---|
| 313 |
|
|---|
| 314 | sfr at 0x80 IOA;
|
|---|
| 315 | sfr at 0x81 SP;
|
|---|
| 316 | sfr at 0x82 DPL;
|
|---|
| 317 | sfr at 0x83 DPH;
|
|---|
| 318 | sfr at 0x84 DPL1;
|
|---|
| 319 | sfr at 0x85 DPH1;
|
|---|
| 320 | sfr at 0x86 DPS;
|
|---|
| 321 | /* DPS */
|
|---|
| 322 | sbit at 0x86+0 SEL;
|
|---|
| 323 | sfr at 0x87 PCON; /* PCON */
|
|---|
| 324 | //sbit IDLE = 0x87+0;
|
|---|
| 325 | //sbit STOP = 0x87+1;
|
|---|
| 326 | //sbit GF0 = 0x87+2;
|
|---|
| 327 | //sbit GF1 = 0x87+3;
|
|---|
| 328 | //sbit SMOD0 = 0x87+7;
|
|---|
| 329 | sfr at 0x88 TCON;
|
|---|
| 330 | /* TCON */
|
|---|
| 331 | sbit at 0x88+0 IT0;
|
|---|
| 332 | sbit at 0x88+1 IE0;
|
|---|
| 333 | sbit at 0x88+2 IT1;
|
|---|
| 334 | sbit at 0x88+3 IE1;
|
|---|
| 335 | sbit at 0x88+4 TR0;
|
|---|
| 336 | sbit at 0x88+5 TF0;
|
|---|
| 337 | sbit at 0x88+6 TR1;
|
|---|
| 338 | sbit at 0x88+7 TF1;
|
|---|
| 339 | sfr at 0x89 TMOD;
|
|---|
| 340 | /* TMOD */
|
|---|
| 341 | //sbit M00 = 0x89+0;
|
|---|
| 342 | //sbit M10 = 0x89+1;
|
|---|
| 343 | //sbit CT0 = 0x89+2;
|
|---|
| 344 | //sbit GATE0 = 0x89+3;
|
|---|
| 345 | //sbit M01 = 0x89+4;
|
|---|
| 346 | //sbit M11 = 0x89+5;
|
|---|
| 347 | //sbit CT1 = 0x89+6;
|
|---|
| 348 | //sbit GATE1 = 0x89+7;
|
|---|
| 349 | sfr at 0x8A TL0;
|
|---|
| 350 | sfr at 0x8B TL1;
|
|---|
| 351 | sfr at 0x8C TH0;
|
|---|
| 352 | sfr at 0x8D TH1;
|
|---|
| 353 | sfr at 0x8E CKCON;
|
|---|
| 354 | /* CKCON */
|
|---|
| 355 | //sbit MD0 = 0x89+0;
|
|---|
| 356 | //sbit MD1 = 0x89+1;
|
|---|
| 357 | //sbit MD2 = 0x89+2;
|
|---|
| 358 | //sbit T0M = 0x89+3;
|
|---|
| 359 | //sbit T1M = 0x89+4;
|
|---|
| 360 | //sbit T2M = 0x89+5;
|
|---|
| 361 | // sfr at 0x8F SPC_FNC; // Was WRS in Reg320
|
|---|
| 362 | /* CKCON */
|
|---|
| 363 | //sbit WRS = 0x8F+0;
|
|---|
| 364 | sfr at 0x90 IOB;
|
|---|
| 365 | sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
|
|---|
| 366 | /* EXIF */
|
|---|
| 367 | //sbit USBINT = 0x91+4;
|
|---|
| 368 | //sbit I2CINT = 0x91+5;
|
|---|
| 369 | //sbit IE4 = 0x91+6;
|
|---|
| 370 | //sbit IE5 = 0x91+7;
|
|---|
| 371 | sfr at 0x92 MPAGE;
|
|---|
| 372 | sfr at 0x98 SCON0;
|
|---|
| 373 | /* SCON0 */
|
|---|
| 374 | sbit at 0x98+0 RI;
|
|---|
| 375 | sbit at 0x98+1 TI;
|
|---|
| 376 | sbit at 0x98+2 RB8;
|
|---|
| 377 | sbit at 0x98+3 TB8;
|
|---|
| 378 | sbit at 0x98+4 REN;
|
|---|
| 379 | sbit at 0x98+5 SM2;
|
|---|
| 380 | sbit at 0x98+6 SM1;
|
|---|
| 381 | sbit at 0x98+7 SM0;
|
|---|
| 382 | sfr at 0x99 SBUF0;
|
|---|
| 383 |
|
|---|
| 384 | sfr at 0x9A APTR1H;
|
|---|
| 385 | sfr at 0x9B APTR1L;
|
|---|
| 386 | sfr at 0x9C AUTODAT1;
|
|---|
| 387 | sfr at 0x9D AUTOPTRH2;
|
|---|
| 388 | sfr at 0x9E AUTOPTRL2;
|
|---|
| 389 | sfr at 0x9F AUTODAT2;
|
|---|
| 390 | sfr at 0xA0 IOC;
|
|---|
| 391 | sfr at 0xA1 INT2CLR;
|
|---|
| 392 | sfr at 0xA2 INT4CLR;
|
|---|
| 393 |
|
|---|
| 394 | #define AUTOPTRH1 APTR1H
|
|---|
| 395 | #define AUTOPTRL1 APTR1L
|
|---|
| 396 |
|
|---|
| 397 | sfr at 0xA8 IE;
|
|---|
| 398 | /* IE */
|
|---|
| 399 | sbit at 0xA8+0 EX0;
|
|---|
| 400 | sbit at 0xA8+1 ET0;
|
|---|
| 401 | sbit at 0xA8+2 EX1;
|
|---|
| 402 | sbit at 0xA8+3 ET1;
|
|---|
| 403 | sbit at 0xA8+4 ES0;
|
|---|
| 404 | sbit at 0xA8+5 ET2;
|
|---|
| 405 | sbit at 0xA8+6 ES1;
|
|---|
| 406 | sbit at 0xA8+7 EA;
|
|---|
| 407 |
|
|---|
| 408 | sfr at 0xAA EP2468STAT;
|
|---|
| 409 | /* EP2468STAT */
|
|---|
| 410 | //sbit EP2E = 0xAA+0;
|
|---|
| 411 | //sbit EP2F = 0xAA+1;
|
|---|
| 412 | //sbit EP4E = 0xAA+2;
|
|---|
| 413 | //sbit EP4F = 0xAA+3;
|
|---|
| 414 | //sbit EP6E = 0xAA+4;
|
|---|
| 415 | //sbit EP6F = 0xAA+5;
|
|---|
| 416 | //sbit EP8E = 0xAA+6;
|
|---|
| 417 | //sbit EP8F = 0xAA+7;
|
|---|
| 418 |
|
|---|
| 419 | sfr at 0xAB EP24FIFOFLGS;
|
|---|
| 420 | sfr at 0xAC EP68FIFOFLGS;
|
|---|
| 421 | sfr at 0xAF AUTOPTRSETUP;
|
|---|
| 422 | /* AUTOPTRSETUP */
|
|---|
| 423 | sbit at 0xAF+0 EXTACC;
|
|---|
| 424 | sbit at 0xAF+1 APTR1FZ;
|
|---|
| 425 | sbit at 0xAF+2 APTR2FZ;
|
|---|
| 426 |
|
|---|
| 427 | sfr at 0xB0 IOD;
|
|---|
| 428 | sfr at 0xB1 IOE;
|
|---|
| 429 | sfr at 0xB2 OEA;
|
|---|
| 430 | sfr at 0xB3 OEB;
|
|---|
| 431 | sfr at 0xB4 OEC;
|
|---|
| 432 | sfr at 0xB5 OED;
|
|---|
| 433 | sfr at 0xB6 OEE;
|
|---|
| 434 |
|
|---|
| 435 | sfr at 0xB8 IP;
|
|---|
| 436 | /* IP */
|
|---|
| 437 | sbit at 0xB8+0 PX0;
|
|---|
| 438 | sbit at 0xB8+1 PT0;
|
|---|
| 439 | sbit at 0xB8+2 PX1;
|
|---|
| 440 | sbit at 0xB8+3 PT1;
|
|---|
| 441 | sbit at 0xB8+4 PS0;
|
|---|
| 442 | sbit at 0xB8+5 PT2;
|
|---|
| 443 | sbit at 0xB8+6 PS1;
|
|---|
| 444 |
|
|---|
| 445 | sfr at 0xBA EP01STAT;
|
|---|
| 446 | sfr at 0xBB GPIFTRIG;
|
|---|
| 447 |
|
|---|
| 448 | sfr at 0xBD GPIFSGLDATH;
|
|---|
| 449 | sfr at 0xBE GPIFSGLDATLX;
|
|---|
| 450 | sfr at 0xBF GPIFSGLDATLNOX;
|
|---|
| 451 |
|
|---|
| 452 | sfr at 0xC0 SCON1;
|
|---|
| 453 | /* SCON1 */
|
|---|
| 454 | sbit at 0xC0+0 RI1;
|
|---|
| 455 | sbit at 0xC0+1 TI1;
|
|---|
| 456 | sbit at 0xC0+2 RB81;
|
|---|
| 457 | sbit at 0xC0+3 TB81;
|
|---|
| 458 | sbit at 0xC0+4 REN1;
|
|---|
| 459 | sbit at 0xC0+5 SM21;
|
|---|
| 460 | sbit at 0xC0+6 SM11;
|
|---|
| 461 | sbit at 0xC0+7 SM01;
|
|---|
| 462 | sfr at 0xC1 SBUF1;
|
|---|
| 463 | sfr at 0xC8 T2CON;
|
|---|
| 464 | /* T2CON */
|
|---|
| 465 | sbit at 0xC8+0 CP_RL2;
|
|---|
| 466 | sbit at 0xC8+1 C_T2;
|
|---|
| 467 | sbit at 0xC8+2 TR2;
|
|---|
| 468 | sbit at 0xC8+3 EXEN2;
|
|---|
| 469 | sbit at 0xC8+4 TCLK;
|
|---|
| 470 | sbit at 0xC8+5 RCLK;
|
|---|
| 471 | sbit at 0xC8+6 EXF2;
|
|---|
| 472 | sbit at 0xC8+7 TF2;
|
|---|
| 473 | sfr at 0xCA RCAP2L;
|
|---|
| 474 | sfr at 0xCB RCAP2H;
|
|---|
| 475 | sfr at 0xCC TL2;
|
|---|
| 476 | sfr at 0xCD TH2;
|
|---|
| 477 | sfr at 0xD0 PSW;
|
|---|
| 478 | /* PSW */
|
|---|
| 479 | sbit at 0xD0+0 P;
|
|---|
| 480 | sbit at 0xD0+1 FL;
|
|---|
| 481 | sbit at 0xD0+2 OV;
|
|---|
| 482 | sbit at 0xD0+3 RS0;
|
|---|
| 483 | sbit at 0xD0+4 RS1;
|
|---|
| 484 | sbit at 0xD0+5 F0;
|
|---|
| 485 | sbit at 0xD0+6 AC;
|
|---|
| 486 | sbit at 0xD0+7 CY;
|
|---|
| 487 | sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320
|
|---|
| 488 | /* EICON */
|
|---|
| 489 | sbit at 0xD8+3 INT6;
|
|---|
| 490 | sbit at 0xD8+4 RESI;
|
|---|
| 491 | sbit at 0xD8+5 ERESI;
|
|---|
| 492 | sbit at 0xD8+7 SMOD1;
|
|---|
| 493 | sfr at 0xE0 ACC;
|
|---|
| 494 | sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
|
|---|
| 495 | /* EIE */
|
|---|
| 496 | sbit at 0xE8+0 EIUSB;
|
|---|
| 497 | sbit at 0xE8+1 EI2C;
|
|---|
| 498 | sbit at 0xE8+2 EIEX4;
|
|---|
| 499 | sbit at 0xE8+3 EIEX5;
|
|---|
| 500 | sbit at 0xE8+4 EIEX6;
|
|---|
| 501 | sfr at 0xF0 B;
|
|---|
| 502 | sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
|
|---|
| 503 | /* EIP */
|
|---|
| 504 | sbit at 0xF8+0 PUSB;
|
|---|
| 505 | sbit at 0xF8+1 PI2C;
|
|---|
| 506 | sbit at 0xF8+2 EIPX4;
|
|---|
| 507 | sbit at 0xF8+3 EIPX5;
|
|---|
| 508 | sbit at 0xF8+4 EIPX6;
|
|---|
| 509 |
|
|---|
| 510 | /*-----------------------------------------------------------------------------
|
|---|
| 511 | Bit Masks
|
|---|
| 512 | -----------------------------------------------------------------------------*/
|
|---|
| 513 |
|
|---|
| 514 | #define bmBIT0 1
|
|---|
| 515 | #define bmBIT1 2
|
|---|
| 516 | #define bmBIT2 4
|
|---|
| 517 | #define bmBIT3 8
|
|---|
| 518 | #define bmBIT4 16
|
|---|
| 519 | #define bmBIT5 32
|
|---|
| 520 | #define bmBIT6 64
|
|---|
| 521 | #define bmBIT7 128
|
|---|
| 522 |
|
|---|
| 523 | /* CPU Control & Status Register (CPUCS) */
|
|---|
| 524 | #define bmPRTCSTB bmBIT5
|
|---|
| 525 | #define bmCLKSPD (bmBIT4 | bmBIT3)
|
|---|
| 526 | #define bmCLKSPD1 bmBIT4
|
|---|
| 527 | #define bmCLKSPD0 bmBIT3
|
|---|
| 528 | #define bmCLKINV bmBIT2
|
|---|
| 529 | #define bmCLKOE bmBIT1
|
|---|
| 530 | #define bm8051RES bmBIT0
|
|---|
| 531 | /* Port Alternate Configuration Registers */
|
|---|
| 532 | /* Port A (PORTACFG) */
|
|---|
| 533 | #define bmFLAGD bmBIT7
|
|---|
| 534 | #define bmINT1 bmBIT1
|
|---|
| 535 | #define bmINT0 bmBIT0
|
|---|
| 536 | /* Port C (PORTCCFG) */
|
|---|
| 537 | #define bmGPIFA7 bmBIT7
|
|---|
| 538 | #define bmGPIFA6 bmBIT6
|
|---|
| 539 | #define bmGPIFA5 bmBIT5
|
|---|
| 540 | #define bmGPIFA4 bmBIT4
|
|---|
| 541 | #define bmGPIFA3 bmBIT3
|
|---|
| 542 | #define bmGPIFA2 bmBIT2
|
|---|
| 543 | #define bmGPIFA1 bmBIT1
|
|---|
| 544 | #define bmGPIFA0 bmBIT0
|
|---|
| 545 | /* Port E (PORTECFG) */
|
|---|
| 546 | #define bmGPIFA8 bmBIT7
|
|---|
| 547 | #define bmT2EX bmBIT6
|
|---|
| 548 | #define bmINT6 bmBIT5
|
|---|
| 549 | #define bmRXD1OUT bmBIT4
|
|---|
| 550 | #define bmRXD0OUT bmBIT3
|
|---|
| 551 | #define bmT2OUT bmBIT2
|
|---|
| 552 | #define bmT1OUT bmBIT1
|
|---|
| 553 | #define bmT0OUT bmBIT0
|
|---|
| 554 |
|
|---|
| 555 | /* I2C Control & Status Register (I2CS) */
|
|---|
| 556 | #define bmSTART bmBIT7
|
|---|
| 557 | #define bmSTOP bmBIT6
|
|---|
| 558 | #define bmLASTRD bmBIT5
|
|---|
| 559 | #define bmID (bmBIT4 | bmBIT3)
|
|---|
| 560 | #define bmBERR bmBIT2
|
|---|
| 561 | #define bmACK bmBIT1
|
|---|
| 562 | #define bmDONE bmBIT0
|
|---|
| 563 | /* I2C Control Register (I2CTL) */
|
|---|
| 564 | #define bmSTOPIE bmBIT1
|
|---|
| 565 | #define bm400KHZ bmBIT0
|
|---|
| 566 | /* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
|
|---|
| 567 | #define bmIV4 bmBIT6
|
|---|
| 568 | #define bmIV3 bmBIT5
|
|---|
| 569 | #define bmIV2 bmBIT4
|
|---|
| 570 | #define bmIV1 bmBIT3
|
|---|
| 571 | #define bmIV0 bmBIT2
|
|---|
| 572 | /* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
|
|---|
| 573 | #define bmEP0ACK bmBIT6
|
|---|
| 574 | #define bmHSGRANT bmBIT5
|
|---|
| 575 | #define bmURES bmBIT4
|
|---|
| 576 | #define bmSUSP bmBIT3
|
|---|
| 577 | #define bmSUTOK bmBIT2
|
|---|
| 578 | #define bmSOF bmBIT1
|
|---|
| 579 | #define bmSUDAV bmBIT0
|
|---|
| 580 | /* Breakpoint register (BREAKPT) */
|
|---|
| 581 | #define bmBREAK bmBIT3
|
|---|
| 582 | #define bmBPPULSE bmBIT2
|
|---|
| 583 | #define bmBPEN bmBIT1
|
|---|
| 584 | /* Interrupt 2 & 4 Setup (INTSETUP) */
|
|---|
| 585 | #define bmAV2EN bmBIT3
|
|---|
| 586 | #define bmINT4IN bmBIT1
|
|---|
| 587 | #define bmAV4EN bmBIT0
|
|---|
| 588 | /* USB Control & Status Register (USBCS) */
|
|---|
| 589 | #define bmHSM bmBIT7
|
|---|
| 590 | #define bmDISCON bmBIT3
|
|---|
| 591 | #define bmNOSYNSOF bmBIT2
|
|---|
| 592 | #define bmRENUM bmBIT1
|
|---|
| 593 | #define bmSIGRESUME bmBIT0
|
|---|
| 594 | /* Wakeup Control and Status Register (WAKEUPCS) */
|
|---|
| 595 | #define bmWU2 bmBIT7
|
|---|
| 596 | #define bmWU bmBIT6
|
|---|
| 597 | #define bmWU2POL bmBIT5
|
|---|
| 598 | #define bmWUPOL bmBIT4
|
|---|
| 599 | #define bmDPEN bmBIT2
|
|---|
| 600 | #define bmWU2EN bmBIT1
|
|---|
| 601 | #define bmWUEN bmBIT0
|
|---|
| 602 | /* End Point 0 Control & Status Register (EP0CS) */
|
|---|
| 603 | #define bmHSNAK bmBIT7
|
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| 604 | /* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
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| 605 | #define bmEPBUSY bmBIT1
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| 606 | #define bmEPSTALL bmBIT0
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| 607 | /* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
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| 608 | #define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
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| 609 | #define bmEPFULL bmBIT3
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| 610 | #define bmEPEMPTY bmBIT2
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| 611 | /* Endpoint Status (EP2468STAT) SFR bits */
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| 612 | #define bmEP8FULL bmBIT7
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| 613 | #define bmEP8EMPTY bmBIT6
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| 614 | #define bmEP6FULL bmBIT5
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| 615 | #define bmEP6EMPTY bmBIT4
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| 616 | #define bmEP4FULL bmBIT3
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| 617 | #define bmEP4EMPTY bmBIT2
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| 618 | #define bmEP2FULL bmBIT1
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| 619 | #define bmEP2EMPTY bmBIT0
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| 620 | /* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
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| 621 | #define bmSDPAUTO bmBIT0
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| 622 | /* Endpoint Data Toggle Control (TOGCTL) */
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| 623 | #define bmQUERYTOGGLE bmBIT7
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| 624 | #define bmSETTOGGLE bmBIT6
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| 625 | #define bmRESETTOGGLE bmBIT5
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| 626 | #define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
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| 627 | /* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
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| 628 | #define bmEP8IBN bmBIT5
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| 629 | #define bmEP6IBN bmBIT4
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| 630 | #define bmEP4IBN bmBIT3
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| 631 | #define bmEP2IBN bmBIT2
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| 632 | #define bmEP1IBN bmBIT1
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| 633 | #define bmEP0IBN bmBIT0
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| 634 |
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| 635 | /* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
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| 636 | #define bmEP8PING bmBIT7
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| 637 | #define bmEP6PING bmBIT6
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| 638 | #define bmEP4PING bmBIT5
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| 639 | #define bmEP2PING bmBIT4
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| 640 | #define bmEP1PING bmBIT3
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| 641 | #define bmEP0PING bmBIT2
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| 642 | #define bmIBN bmBIT0
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| 643 |
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| 644 | /* Interface Configuration bits (IFCONFIG) */
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|---|
| 645 | #define bmIFCLKSRC bmBIT7 // set == INTERNAL
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| 646 | #define bm3048MHZ bmBIT6 // set == 48 MHz
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| 647 | #define bmIFCLKOE bmBIT5
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|---|
| 648 | #define bmIFCLKPOL bmBIT4
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| 649 | #define bmASYNC bmBIT3
|
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| 650 | #define bmGSTATE bmBIT2
|
|---|
| 651 | #define bmIFCFG1 bmBIT1
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| 652 | #define bmIFCFG0 bmBIT0
|
|---|
| 653 | #define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
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| 654 | #define bmIFGPIF bmIFCFG1
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|---|
| 655 |
|
|---|
| 656 | /* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
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| 657 | #define bmINFM bmBIT6
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|---|
| 658 | #define bmOEP bmBIT5
|
|---|
| 659 | #define bmAUTOOUT bmBIT4
|
|---|
| 660 | #define bmAUTOIN bmBIT3
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|---|
| 661 | #define bmZEROLENIN bmBIT2
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|---|
| 662 | // must be zero bmBIT1
|
|---|
| 663 | #define bmWORDWIDE bmBIT0
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|---|
| 664 |
|
|---|
| 665 | /*
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|---|
| 666 | * Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
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|---|
| 667 | */
|
|---|
| 668 | #define bmNOAUTOARM bmBIT1 // these don't match the docs
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|---|
| 669 | #define bmSKIPCOMMIT bmBIT0 // these don't match the docs
|
|---|
| 670 |
|
|---|
| 671 | #define bmDYN_OUT bmBIT1 // these do...
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|---|
| 672 | #define bmENH_PKT bmBIT0
|
|---|
| 673 |
|
|---|
| 674 |
|
|---|
| 675 | /* Fifo Reset bits (FIFORESET) */
|
|---|
| 676 | #define bmNAKALL bmBIT7
|
|---|
| 677 |
|
|---|
| 678 | /* Endpoint Configuration (EPxCFG) */
|
|---|
| 679 | #define bmVALID bmBIT7
|
|---|
| 680 | #define bmIN bmBIT6
|
|---|
| 681 | #define bmTYPE1 bmBIT5
|
|---|
| 682 | #define bmTYPE0 bmBIT4
|
|---|
| 683 | #define bmISOCHRONOUS bmTYPE0
|
|---|
| 684 | #define bmBULK bmTYPE1
|
|---|
| 685 | #define bmINTERRUPT (bmTYPE1 | bmTYPE0)
|
|---|
| 686 | #define bm1KBUF bmBIT3
|
|---|
| 687 | #define bmBUF1 bmBIT1
|
|---|
| 688 | #define bmBUF0 bmBIT0
|
|---|
| 689 | #define bmQUADBUF 0
|
|---|
| 690 | #define bmINVALIDBUF bmBUF0
|
|---|
| 691 | #define bmDOUBLEBUF bmBUF1
|
|---|
| 692 | #define bmTRIPLEBUF (bmBUF1 | bmBUF0)
|
|---|
| 693 |
|
|---|
| 694 | /* OUTPKTEND */
|
|---|
| 695 | #define bmSKIP bmBIT7 // low 4 bits specify which end point
|
|---|
| 696 |
|
|---|
| 697 | /* GPIFTRIG defs */
|
|---|
| 698 | #define bmGPIF_IDLE bmBIT7 // status bit
|
|---|
| 699 |
|
|---|
| 700 | #define bmGPIF_EP2_START 0
|
|---|
| 701 | #define bmGPIF_EP4_START 1
|
|---|
| 702 | #define bmGPIF_EP6_START 2
|
|---|
| 703 | #define bmGPIF_EP8_START 3
|
|---|
| 704 | #define bmGPIF_READ bmBIT2
|
|---|
| 705 | #define bmGPIF_WRITE 0
|
|---|
| 706 |
|
|---|
| 707 | /* EXIF bits */
|
|---|
| 708 | #define bmEXIF_USBINT bmBIT4
|
|---|
| 709 | #define bmEXIF_I2CINT bmBIT5
|
|---|
| 710 | #define bmEXIF_IE4 bmBIT6
|
|---|
| 711 | #define bmEXIF_IE5 bmBIT7
|
|---|
| 712 |
|
|---|
| 713 |
|
|---|
| 714 | #endif /* FX2REGS_H */
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