source: trunk/FirmwareFX2/fx2/fx2regs.h@ 103

Last change on this file since 103 was 4, checked in by demin, 15 years ago

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[4]1/* -*- c++ -*- */
2/*-----------------------------------------------------------------------------
3 * FX2 register definitions
4 *-----------------------------------------------------------------------------
5 * Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
6 * Copyright 2003 Free Software Foundation, Inc.
7 *-----------------------------------------------------------------------------
8 * This code is part of usbjtag. usbjtag is free software; you can redistribute
9 * it and/or modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the License,
11 * or (at your option) any later version. usbjtag is distributed in the hope
12 * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
13 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. You should have received a
15 * copy of the GNU General Public License along with this program in the file
16 * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
17 * St, Fifth Floor, Boston, MA 02110-1301 USA
18 *-----------------------------------------------------------------------------
19 */
20
21/*
22//-----------------------------------------------------------------------------
23// File: FX2regs.h
24// Contents: EZ-USB FX2 register declarations and bit mask definitions.
25//
26// $Archive: /USB/Target/Inc/fx2regs.h $
27// $Date: 2009-08-26 09:14:41 $
28// $Revision: 1.1 $
29//
30//
31// Copyright (c) 2000 Cypress Semiconductor, All rights reserved
32//-----------------------------------------------------------------------------
33*/
34
35
36#ifndef FX2REGS_H /* Header Sentry */
37#define FX2REGS_H
38
39#define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h
40
41/*
42//-----------------------------------------------------------------------------
43// FX2 Related Register Assignments
44//-----------------------------------------------------------------------------
45
46// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
47// address allocation by using "#define ALLOCATE_EXTERN".
48// When using "#define ALLOCATE_EXTERN", you get (for instance):
49// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
50// Such lines are created from FX2.h by using the preprocessor.
51// Incidently, these lines will not generate any space in the resulting hex
52// file; they just bind the symbols to the addresses for compilation.
53// You just need to put "#define ALLOCATE_EXTERN" in your main program file;
54// i.e. fw.c or a stand-alone C source file.
55// Without "#define ALLOCATE_EXTERN", you just get the external reference:
56// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
57// This uses the concatenation operator "##" to insert a comment "//"
58// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
59*/
60
61
62#ifdef ALLOCATE_EXTERN
63#define EXTERN
64#define _AT_(a) at a
65#else
66#define EXTERN extern
67#define _AT_ ;/ ## /
68#endif
69
70typedef unsigned char BYTE;
71typedef unsigned short WORD;
72
73EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];
74EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
75
76// General Configuration
77
78EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
79EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
80EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
81EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
82EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
83EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
84EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
85EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
86EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
87EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
88EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
89EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
90
91// Endpoint Configuration
92
93EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
94EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
95EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
96EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
97EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
98EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
99EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
100EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
101EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
102EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
103EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
104EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
105EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
106EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
107EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
108EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
109EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
110EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
111EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
112EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
113EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
114EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
115EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
116EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
117EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
118EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
119EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
120EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
121EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
122EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
123EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
124EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
125
126// Interrupts
127
128EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
129EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
130EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
131EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
132EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
133EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
134EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
135EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
136EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
137EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
138EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
139EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
140EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
141EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
142EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
143EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
144EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
145EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
146EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
147EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
148EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
149EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
150EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
151EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
152EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
153
154// Input/Output
155
156EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
157EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
158EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
159EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
160EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
161EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
162EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
163EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
164
165#define EXTAUTODAT1 XAUTODAT1
166#define EXTAUTODAT2 XAUTODAT2
167
168// USB Control
169
170EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
171EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
172EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
173EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
174EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
175EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
176EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
177EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
178
179// Endpoints
180
181EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
182EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
183EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
184EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
185EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
186EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
187EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
188EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
189EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
190EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
191EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
192EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
193EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
194EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
195EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
196EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
197EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
198EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
199EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
200EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
201EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
202EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
203EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
204EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
205EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
206EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
207EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
208EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
209EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
210EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
211EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
212EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
213EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
214EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
215EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
216
217// GPIF
218
219EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
220EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
221EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
222EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
223EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
224EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
225
226EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
227EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
228EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
229EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
230
231#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
232#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
233#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility
234#define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
235#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility
236#define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
237#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
238#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
239
240// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
241// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
242EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
243EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
244EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
245// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
246// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
247EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
248EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
249EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
250// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
251// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
252EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
253EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
254EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
255// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
256// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
257EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
258EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
259EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
260EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
261EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
262EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
263EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
264EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
265EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
266
267// UDMA
268
269EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
270EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
271EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
272EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
273EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
274EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
275EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
276EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
277EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
278EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
279EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
280EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
281
282
283// Debug/Test
284
285EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
286EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
287EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
288EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
289EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
290EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
291EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
292
293// Endpoint Buffers
294
295EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
296EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
297EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
298EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
299EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
300EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
301EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
302
303#undef EXTERN
304#undef _AT_
305
306/*-----------------------------------------------------------------------------
307 Special Function Registers (SFRs)
308 The byte registers and bits defined in the following list are based
309 on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
310 If you modify the register definitions below, please regenerate the file
311 "ezregs.inc" which includes the same basic information for assembly inclusion.
312-----------------------------------------------------------------------------*/
313
314sfr at 0x80 IOA;
315sfr at 0x81 SP;
316sfr at 0x82 DPL;
317sfr at 0x83 DPH;
318sfr at 0x84 DPL1;
319sfr at 0x85 DPH1;
320sfr at 0x86 DPS;
321 /* DPS */
322 sbit at 0x86+0 SEL;
323sfr at 0x87 PCON; /* PCON */
324 //sbit IDLE = 0x87+0;
325 //sbit STOP = 0x87+1;
326 //sbit GF0 = 0x87+2;
327 //sbit GF1 = 0x87+3;
328 //sbit SMOD0 = 0x87+7;
329sfr at 0x88 TCON;
330 /* TCON */
331 sbit at 0x88+0 IT0;
332 sbit at 0x88+1 IE0;
333 sbit at 0x88+2 IT1;
334 sbit at 0x88+3 IE1;
335 sbit at 0x88+4 TR0;
336 sbit at 0x88+5 TF0;
337 sbit at 0x88+6 TR1;
338 sbit at 0x88+7 TF1;
339sfr at 0x89 TMOD;
340 /* TMOD */
341 //sbit M00 = 0x89+0;
342 //sbit M10 = 0x89+1;
343 //sbit CT0 = 0x89+2;
344 //sbit GATE0 = 0x89+3;
345 //sbit M01 = 0x89+4;
346 //sbit M11 = 0x89+5;
347 //sbit CT1 = 0x89+6;
348 //sbit GATE1 = 0x89+7;
349sfr at 0x8A TL0;
350sfr at 0x8B TL1;
351sfr at 0x8C TH0;
352sfr at 0x8D TH1;
353sfr at 0x8E CKCON;
354 /* CKCON */
355 //sbit MD0 = 0x89+0;
356 //sbit MD1 = 0x89+1;
357 //sbit MD2 = 0x89+2;
358 //sbit T0M = 0x89+3;
359 //sbit T1M = 0x89+4;
360 //sbit T2M = 0x89+5;
361// sfr at 0x8F SPC_FNC; // Was WRS in Reg320
362 /* CKCON */
363 //sbit WRS = 0x8F+0;
364sfr at 0x90 IOB;
365sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
366 /* EXIF */
367 //sbit USBINT = 0x91+4;
368 //sbit I2CINT = 0x91+5;
369 //sbit IE4 = 0x91+6;
370 //sbit IE5 = 0x91+7;
371sfr at 0x92 MPAGE;
372sfr at 0x98 SCON0;
373 /* SCON0 */
374 sbit at 0x98+0 RI;
375 sbit at 0x98+1 TI;
376 sbit at 0x98+2 RB8;
377 sbit at 0x98+3 TB8;
378 sbit at 0x98+4 REN;
379 sbit at 0x98+5 SM2;
380 sbit at 0x98+6 SM1;
381 sbit at 0x98+7 SM0;
382sfr at 0x99 SBUF0;
383
384sfr at 0x9A APTR1H;
385sfr at 0x9B APTR1L;
386sfr at 0x9C AUTODAT1;
387sfr at 0x9D AUTOPTRH2;
388sfr at 0x9E AUTOPTRL2;
389sfr at 0x9F AUTODAT2;
390sfr at 0xA0 IOC;
391sfr at 0xA1 INT2CLR;
392sfr at 0xA2 INT4CLR;
393
394#define AUTOPTRH1 APTR1H
395#define AUTOPTRL1 APTR1L
396
397sfr at 0xA8 IE;
398 /* IE */
399 sbit at 0xA8+0 EX0;
400 sbit at 0xA8+1 ET0;
401 sbit at 0xA8+2 EX1;
402 sbit at 0xA8+3 ET1;
403 sbit at 0xA8+4 ES0;
404 sbit at 0xA8+5 ET2;
405 sbit at 0xA8+6 ES1;
406 sbit at 0xA8+7 EA;
407
408sfr at 0xAA EP2468STAT;
409 /* EP2468STAT */
410 //sbit EP2E = 0xAA+0;
411 //sbit EP2F = 0xAA+1;
412 //sbit EP4E = 0xAA+2;
413 //sbit EP4F = 0xAA+3;
414 //sbit EP6E = 0xAA+4;
415 //sbit EP6F = 0xAA+5;
416 //sbit EP8E = 0xAA+6;
417 //sbit EP8F = 0xAA+7;
418
419sfr at 0xAB EP24FIFOFLGS;
420sfr at 0xAC EP68FIFOFLGS;
421sfr at 0xAF AUTOPTRSETUP;
422 /* AUTOPTRSETUP */
423 sbit at 0xAF+0 EXTACC;
424 sbit at 0xAF+1 APTR1FZ;
425 sbit at 0xAF+2 APTR2FZ;
426
427sfr at 0xB0 IOD;
428sfr at 0xB1 IOE;
429sfr at 0xB2 OEA;
430sfr at 0xB3 OEB;
431sfr at 0xB4 OEC;
432sfr at 0xB5 OED;
433sfr at 0xB6 OEE;
434
435sfr at 0xB8 IP;
436 /* IP */
437 sbit at 0xB8+0 PX0;
438 sbit at 0xB8+1 PT0;
439 sbit at 0xB8+2 PX1;
440 sbit at 0xB8+3 PT1;
441 sbit at 0xB8+4 PS0;
442 sbit at 0xB8+5 PT2;
443 sbit at 0xB8+6 PS1;
444
445sfr at 0xBA EP01STAT;
446sfr at 0xBB GPIFTRIG;
447
448sfr at 0xBD GPIFSGLDATH;
449sfr at 0xBE GPIFSGLDATLX;
450sfr at 0xBF GPIFSGLDATLNOX;
451
452sfr at 0xC0 SCON1;
453 /* SCON1 */
454 sbit at 0xC0+0 RI1;
455 sbit at 0xC0+1 TI1;
456 sbit at 0xC0+2 RB81;
457 sbit at 0xC0+3 TB81;
458 sbit at 0xC0+4 REN1;
459 sbit at 0xC0+5 SM21;
460 sbit at 0xC0+6 SM11;
461 sbit at 0xC0+7 SM01;
462sfr at 0xC1 SBUF1;
463sfr at 0xC8 T2CON;
464 /* T2CON */
465 sbit at 0xC8+0 CP_RL2;
466 sbit at 0xC8+1 C_T2;
467 sbit at 0xC8+2 TR2;
468 sbit at 0xC8+3 EXEN2;
469 sbit at 0xC8+4 TCLK;
470 sbit at 0xC8+5 RCLK;
471 sbit at 0xC8+6 EXF2;
472 sbit at 0xC8+7 TF2;
473sfr at 0xCA RCAP2L;
474sfr at 0xCB RCAP2H;
475sfr at 0xCC TL2;
476sfr at 0xCD TH2;
477sfr at 0xD0 PSW;
478 /* PSW */
479 sbit at 0xD0+0 P;
480 sbit at 0xD0+1 FL;
481 sbit at 0xD0+2 OV;
482 sbit at 0xD0+3 RS0;
483 sbit at 0xD0+4 RS1;
484 sbit at 0xD0+5 F0;
485 sbit at 0xD0+6 AC;
486 sbit at 0xD0+7 CY;
487sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320
488 /* EICON */
489 sbit at 0xD8+3 INT6;
490 sbit at 0xD8+4 RESI;
491 sbit at 0xD8+5 ERESI;
492 sbit at 0xD8+7 SMOD1;
493sfr at 0xE0 ACC;
494sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
495 /* EIE */
496 sbit at 0xE8+0 EIUSB;
497 sbit at 0xE8+1 EI2C;
498 sbit at 0xE8+2 EIEX4;
499 sbit at 0xE8+3 EIEX5;
500 sbit at 0xE8+4 EIEX6;
501sfr at 0xF0 B;
502sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
503 /* EIP */
504 sbit at 0xF8+0 PUSB;
505 sbit at 0xF8+1 PI2C;
506 sbit at 0xF8+2 EIPX4;
507 sbit at 0xF8+3 EIPX5;
508 sbit at 0xF8+4 EIPX6;
509
510/*-----------------------------------------------------------------------------
511 Bit Masks
512-----------------------------------------------------------------------------*/
513
514#define bmBIT0 1
515#define bmBIT1 2
516#define bmBIT2 4
517#define bmBIT3 8
518#define bmBIT4 16
519#define bmBIT5 32
520#define bmBIT6 64
521#define bmBIT7 128
522
523/* CPU Control & Status Register (CPUCS) */
524#define bmPRTCSTB bmBIT5
525#define bmCLKSPD (bmBIT4 | bmBIT3)
526#define bmCLKSPD1 bmBIT4
527#define bmCLKSPD0 bmBIT3
528#define bmCLKINV bmBIT2
529#define bmCLKOE bmBIT1
530#define bm8051RES bmBIT0
531/* Port Alternate Configuration Registers */
532/* Port A (PORTACFG) */
533#define bmFLAGD bmBIT7
534#define bmINT1 bmBIT1
535#define bmINT0 bmBIT0
536/* Port C (PORTCCFG) */
537#define bmGPIFA7 bmBIT7
538#define bmGPIFA6 bmBIT6
539#define bmGPIFA5 bmBIT5
540#define bmGPIFA4 bmBIT4
541#define bmGPIFA3 bmBIT3
542#define bmGPIFA2 bmBIT2
543#define bmGPIFA1 bmBIT1
544#define bmGPIFA0 bmBIT0
545/* Port E (PORTECFG) */
546#define bmGPIFA8 bmBIT7
547#define bmT2EX bmBIT6
548#define bmINT6 bmBIT5
549#define bmRXD1OUT bmBIT4
550#define bmRXD0OUT bmBIT3
551#define bmT2OUT bmBIT2
552#define bmT1OUT bmBIT1
553#define bmT0OUT bmBIT0
554
555/* I2C Control & Status Register (I2CS) */
556#define bmSTART bmBIT7
557#define bmSTOP bmBIT6
558#define bmLASTRD bmBIT5
559#define bmID (bmBIT4 | bmBIT3)
560#define bmBERR bmBIT2
561#define bmACK bmBIT1
562#define bmDONE bmBIT0
563/* I2C Control Register (I2CTL) */
564#define bmSTOPIE bmBIT1
565#define bm400KHZ bmBIT0
566/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
567#define bmIV4 bmBIT6
568#define bmIV3 bmBIT5
569#define bmIV2 bmBIT4
570#define bmIV1 bmBIT3
571#define bmIV0 bmBIT2
572/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
573#define bmEP0ACK bmBIT6
574#define bmHSGRANT bmBIT5
575#define bmURES bmBIT4
576#define bmSUSP bmBIT3
577#define bmSUTOK bmBIT2
578#define bmSOF bmBIT1
579#define bmSUDAV bmBIT0
580/* Breakpoint register (BREAKPT) */
581#define bmBREAK bmBIT3
582#define bmBPPULSE bmBIT2
583#define bmBPEN bmBIT1
584/* Interrupt 2 & 4 Setup (INTSETUP) */
585#define bmAV2EN bmBIT3
586#define bmINT4IN bmBIT1
587#define bmAV4EN bmBIT0
588/* USB Control & Status Register (USBCS) */
589#define bmHSM bmBIT7
590#define bmDISCON bmBIT3
591#define bmNOSYNSOF bmBIT2
592#define bmRENUM bmBIT1
593#define bmSIGRESUME bmBIT0
594/* Wakeup Control and Status Register (WAKEUPCS) */
595#define bmWU2 bmBIT7
596#define bmWU bmBIT6
597#define bmWU2POL bmBIT5
598#define bmWUPOL bmBIT4
599#define bmDPEN bmBIT2
600#define bmWU2EN bmBIT1
601#define bmWUEN bmBIT0
602/* End Point 0 Control & Status Register (EP0CS) */
603#define bmHSNAK bmBIT7
604/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
605#define bmEPBUSY bmBIT1
606#define bmEPSTALL bmBIT0
607/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
608#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
609#define bmEPFULL bmBIT3
610#define bmEPEMPTY bmBIT2
611/* Endpoint Status (EP2468STAT) SFR bits */
612#define bmEP8FULL bmBIT7
613#define bmEP8EMPTY bmBIT6
614#define bmEP6FULL bmBIT5
615#define bmEP6EMPTY bmBIT4
616#define bmEP4FULL bmBIT3
617#define bmEP4EMPTY bmBIT2
618#define bmEP2FULL bmBIT1
619#define bmEP2EMPTY bmBIT0
620/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
621#define bmSDPAUTO bmBIT0
622/* Endpoint Data Toggle Control (TOGCTL) */
623#define bmQUERYTOGGLE bmBIT7
624#define bmSETTOGGLE bmBIT6
625#define bmRESETTOGGLE bmBIT5
626#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
627/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
628#define bmEP8IBN bmBIT5
629#define bmEP6IBN bmBIT4
630#define bmEP4IBN bmBIT3
631#define bmEP2IBN bmBIT2
632#define bmEP1IBN bmBIT1
633#define bmEP0IBN bmBIT0
634
635/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
636#define bmEP8PING bmBIT7
637#define bmEP6PING bmBIT6
638#define bmEP4PING bmBIT5
639#define bmEP2PING bmBIT4
640#define bmEP1PING bmBIT3
641#define bmEP0PING bmBIT2
642#define bmIBN bmBIT0
643
644/* Interface Configuration bits (IFCONFIG) */
645#define bmIFCLKSRC bmBIT7 // set == INTERNAL
646#define bm3048MHZ bmBIT6 // set == 48 MHz
647#define bmIFCLKOE bmBIT5
648#define bmIFCLKPOL bmBIT4
649#define bmASYNC bmBIT3
650#define bmGSTATE bmBIT2
651#define bmIFCFG1 bmBIT1
652#define bmIFCFG0 bmBIT0
653#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
654#define bmIFGPIF bmIFCFG1
655
656/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
657#define bmINFM bmBIT6
658#define bmOEP bmBIT5
659#define bmAUTOOUT bmBIT4
660#define bmAUTOIN bmBIT3
661#define bmZEROLENIN bmBIT2
662// must be zero bmBIT1
663#define bmWORDWIDE bmBIT0
664
665/*
666 * Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
667 */
668#define bmNOAUTOARM bmBIT1 // these don't match the docs
669#define bmSKIPCOMMIT bmBIT0 // these don't match the docs
670
671#define bmDYN_OUT bmBIT1 // these do...
672#define bmENH_PKT bmBIT0
673
674
675/* Fifo Reset bits (FIFORESET) */
676#define bmNAKALL bmBIT7
677
678/* Endpoint Configuration (EPxCFG) */
679#define bmVALID bmBIT7
680#define bmIN bmBIT6
681#define bmTYPE1 bmBIT5
682#define bmTYPE0 bmBIT4
683#define bmISOCHRONOUS bmTYPE0
684#define bmBULK bmTYPE1
685#define bmINTERRUPT (bmTYPE1 | bmTYPE0)
686#define bm1KBUF bmBIT3
687#define bmBUF1 bmBIT1
688#define bmBUF0 bmBIT0
689#define bmQUADBUF 0
690#define bmINVALIDBUF bmBUF0
691#define bmDOUBLEBUF bmBUF1
692#define bmTRIPLEBUF (bmBUF1 | bmBUF0)
693
694/* OUTPKTEND */
695#define bmSKIP bmBIT7 // low 4 bits specify which end point
696
697/* GPIFTRIG defs */
698#define bmGPIF_IDLE bmBIT7 // status bit
699
700#define bmGPIF_EP2_START 0
701#define bmGPIF_EP4_START 1
702#define bmGPIF_EP6_START 2
703#define bmGPIF_EP8_START 3
704#define bmGPIF_READ bmBIT2
705#define bmGPIF_WRITE 0
706
707/* EXIF bits */
708#define bmEXIF_USBINT bmBIT4
709#define bmEXIF_I2CINT bmBIT5
710#define bmEXIF_IE4 bmBIT6
711#define bmEXIF_IE5 bmBIT7
712
713
714#endif /* FX2REGS_H */
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