1 | module top
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2 | (
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3 | input wire CLK_100MHz,
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4 | output wire LED,
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5 |
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6 | input wire ADC_DCO,
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7 | input wire ADC_FCO,
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8 | input wire [5:0] ADC_D,
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9 |
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10 | output wire USB_SLRD,
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11 | output wire USB_SLWR,
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12 | input wire USB_IFCLK,
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13 | input wire USB_FLAGA, // EMPTY flag for EP6
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14 | input wire USB_FLAGB, // FULL flag for EP8
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15 | output wire USB_PA2,
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16 | output wire USB_PA4,
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17 | output wire USB_PA6,
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18 | inout wire [7:0] USB_PB,
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19 |
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20 | output wire RAM_CLK,
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21 | output wire RAM_WE,
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22 | output wire [21:0] RAM_ADDR,
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23 | inout wire RAM_DQAP,
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24 | inout wire [7:0] RAM_DQA,
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25 | inout wire RAM_DQBP,
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26 | inout wire [7:0] RAM_DQB
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27 | );
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28 |
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29 | // Turn output ports off
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30 | /*
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31 | assign RAM_CLK = 1'b0;
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32 | assign RAM_CE1 = 1'b0;
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33 | assign RAM_WE = 1'b0;
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34 | assign RAM_ADDR = 20'h00000;
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35 | */
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36 |
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37 | assign RAM_CLK = sys_clock;
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38 |
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39 | assign USB_PA2 = ~usb_rden;
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40 | assign USB_PA4 = usb_addr;
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41 | assign USB_PA6 = ~usb_pktend;
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42 |
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43 | wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
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44 | wire usb_tx_wrreq, usb_rx_rdreq;
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45 | wire usb_tx_full, usb_rx_empty;
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46 | wire [7:0] usb_tx_data, usb_rx_data;
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47 | wire usb_addr;
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48 |
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49 | assign USB_SLRD = ~usb_rdreq;
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50 | assign USB_SLWR = ~usb_wrreq;
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51 |
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52 | usb_fifo usb_unit
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53 | (
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54 | .usb_clock(USB_IFCLK),
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55 | .usb_data(USB_PB),
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56 | .usb_full(~USB_FLAGB),
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57 | .usb_empty(~USB_FLAGA),
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58 | .usb_wrreq(usb_wrreq),
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59 | .usb_rdreq(usb_rdreq),
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60 | .usb_rden(usb_rden),
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61 | .usb_pktend(usb_pktend),
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62 | .usb_addr(usb_addr),
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63 |
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64 | .clock(sys_clock),
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65 |
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66 | .tx_full(usb_tx_full),
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67 | .tx_wrreq(usb_tx_wrreq),
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68 | .tx_data(usb_tx_data),
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69 |
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70 | .rx_empty(usb_rx_empty),
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71 | .rx_rdreq(usb_rx_rdreq),
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72 | .rx_q(usb_rx_data)
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73 | );
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74 |
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75 | wire sys_clock;
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76 |
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77 | sys_pll sys_pll_unit(
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78 | .inclk0(CLK_100MHz),
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79 | .c0(sys_clock));
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80 |
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81 | wire [15:0] cfg_bits [63:0];
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82 | wire [1023:0] int_cfg_bits;
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83 |
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84 | wire cfg_reset;
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85 |
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86 | wire [2:0] bus_ssel;
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87 | wire bus_wren;
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88 | wire [31:0] bus_addr;
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89 | wire [15:0] bus_mosi;
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90 | wire [15:0] bus_miso [2:0];
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91 | wire [2:0] bus_busy;
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92 |
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93 | wire [15:0] mrg_bus_miso;
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94 | wire mrg_bus_busy;
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95 |
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96 | wire [3*16-1:0] int_bus_miso;
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97 |
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98 | genvar j;
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99 |
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100 | generate
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101 | for (j = 0; j < 64; j = j + 1)
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102 | begin : CONFIGURATION_OUTPUT
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103 | assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
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104 | end
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105 | endgenerate
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106 |
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107 | configuration configuration_unit (
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108 | .clock(sys_clock),
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109 | .reset(cfg_reset),
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110 | .bus_ssel(bus_ssel[0]),
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111 | .bus_wren(bus_wren),
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112 | .bus_addr(bus_addr[5:0]),
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113 | .bus_mosi(bus_mosi),
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114 | .bus_miso(bus_miso[0]),
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115 | .bus_busy(bus_busy[0]),
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116 | .cfg_bits(int_cfg_bits));
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117 |
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118 | generate
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119 | for (j = 0; j < 3; j = j + 1)
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120 | begin : BUS_OUTPUT
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121 | assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
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122 | end
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123 | endgenerate
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124 |
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125 | lpm_mux #(
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126 | .lpm_size(3),
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127 | .lpm_type("LPM_MUX"),
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128 | .lpm_width(16),
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129 | .lpm_widths(2)) bus_miso_mux_unit (
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130 | .sel(bus_addr[29:28]),
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131 | .data(int_bus_miso),
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132 | .result(mrg_bus_miso));
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133 |
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134 | lpm_mux #(
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135 | .lpm_size(3),
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136 | .lpm_type("LPM_MUX"),
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137 | .lpm_width(1),
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138 | .lpm_widths(2)) bus_busy_mux_unit (
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139 | .sel(bus_addr[29:28]),
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140 | .data(bus_busy),
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141 | .result(mrg_bus_busy));
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142 |
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143 | lpm_decode #(
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144 | .lpm_decodes(3),
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145 | .lpm_type("LPM_DECODE"),
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146 | .lpm_width(2)) lpm_decode_unit (
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147 | .data(bus_addr[29:28]),
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148 | .eq(bus_ssel));
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149 |
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150 |
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151 | control control_unit (
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152 | .clock(sys_clock),
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153 | .rx_empty(usb_rx_empty),
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154 | .tx_full(usb_tx_full),
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155 | .rx_data(usb_rx_data),
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156 | .rx_rdreq(usb_rx_rdreq),
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157 | .tx_wrreq(usb_tx_wrreq),
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158 | .tx_data(usb_tx_data),
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159 | .bus_wren(bus_wren),
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160 | .bus_addr(bus_addr),
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161 | .bus_mosi(bus_mosi),
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162 | .bus_miso(mrg_bus_miso),
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163 | .bus_busy(mrg_bus_busy),
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164 | .led(LED));
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165 |
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166 | endmodule
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