source: trunk/BandeCosmique/top.v

Last change on this file was 201, checked in by demin, 10 years ago

remove unneeded wires, regs and modules
File size: 3.3 KB
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[200]1module top
2 (
3 input wire CLK_100MHz,
4 output wire LED,
5
6 input wire ADC_DCO,
7 input wire ADC_FCO,
8 input wire [5:0] ADC_D,
9
10 output wire USB_SLRD,
11 output wire USB_SLWR,
12 input wire USB_IFCLK,
13 input wire USB_FLAGA, // EMPTY flag for EP6
14 input wire USB_FLAGB, // FULL flag for EP8
15 output wire USB_PA2,
16 output wire USB_PA4,
17 output wire USB_PA6,
18 inout wire [7:0] USB_PB,
19
20 output wire RAM_CLK,
21 output wire RAM_WE,
22 output wire [21:0] RAM_ADDR,
23 inout wire RAM_DQAP,
24 inout wire [7:0] RAM_DQA,
25 inout wire RAM_DQBP,
26 inout wire [7:0] RAM_DQB
27 );
28
29 // Turn output ports off
30/*
31 assign RAM_CLK = 1'b0;
32 assign RAM_CE1 = 1'b0;
33 assign RAM_WE = 1'b0;
34 assign RAM_ADDR = 20'h00000;
35*/
36
37 assign RAM_CLK = sys_clock;
38
39 assign USB_PA2 = ~usb_rden;
40 assign USB_PA4 = usb_addr;
41 assign USB_PA6 = ~usb_pktend;
42
43 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
44 wire usb_tx_wrreq, usb_rx_rdreq;
45 wire usb_tx_full, usb_rx_empty;
46 wire [7:0] usb_tx_data, usb_rx_data;
47 wire usb_addr;
48
49 assign USB_SLRD = ~usb_rdreq;
50 assign USB_SLWR = ~usb_wrreq;
51
52 usb_fifo usb_unit
53 (
54 .usb_clock(USB_IFCLK),
55 .usb_data(USB_PB),
56 .usb_full(~USB_FLAGB),
57 .usb_empty(~USB_FLAGA),
58 .usb_wrreq(usb_wrreq),
59 .usb_rdreq(usb_rdreq),
60 .usb_rden(usb_rden),
61 .usb_pktend(usb_pktend),
62 .usb_addr(usb_addr),
63
64 .clock(sys_clock),
65
66 .tx_full(usb_tx_full),
67 .tx_wrreq(usb_tx_wrreq),
68 .tx_data(usb_tx_data),
69
70 .rx_empty(usb_rx_empty),
71 .rx_rdreq(usb_rx_rdreq),
72 .rx_q(usb_rx_data)
73 );
74
[201]75 wire sys_clock;
[200]76
77 sys_pll sys_pll_unit(
78 .inclk0(CLK_100MHz),
79 .c0(sys_clock));
80
81 wire [15:0] cfg_bits [63:0];
82 wire [1023:0] int_cfg_bits;
83
84 wire cfg_reset;
85
86 wire [2:0] bus_ssel;
87 wire bus_wren;
88 wire [31:0] bus_addr;
89 wire [15:0] bus_mosi;
90 wire [15:0] bus_miso [2:0];
91 wire [2:0] bus_busy;
92
93 wire [15:0] mrg_bus_miso;
94 wire mrg_bus_busy;
95
96 wire [3*16-1:0] int_bus_miso;
97
98 genvar j;
99
100 generate
101 for (j = 0; j < 64; j = j + 1)
102 begin : CONFIGURATION_OUTPUT
103 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
104 end
105 endgenerate
106
107 configuration configuration_unit (
108 .clock(sys_clock),
109 .reset(cfg_reset),
110 .bus_ssel(bus_ssel[0]),
111 .bus_wren(bus_wren),
112 .bus_addr(bus_addr[5:0]),
113 .bus_mosi(bus_mosi),
114 .bus_miso(bus_miso[0]),
115 .bus_busy(bus_busy[0]),
[201]116 .cfg_bits(int_cfg_bits));
[200]117
118 generate
119 for (j = 0; j < 3; j = j + 1)
120 begin : BUS_OUTPUT
121 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
122 end
123 endgenerate
124
125 lpm_mux #(
126 .lpm_size(3),
127 .lpm_type("LPM_MUX"),
128 .lpm_width(16),
129 .lpm_widths(2)) bus_miso_mux_unit (
130 .sel(bus_addr[29:28]),
131 .data(int_bus_miso),
132 .result(mrg_bus_miso));
133
134 lpm_mux #(
135 .lpm_size(3),
136 .lpm_type("LPM_MUX"),
137 .lpm_width(1),
138 .lpm_widths(2)) bus_busy_mux_unit (
139 .sel(bus_addr[29:28]),
140 .data(bus_busy),
141 .result(mrg_bus_busy));
142
143 lpm_decode #(
144 .lpm_decodes(3),
145 .lpm_type("LPM_DECODE"),
146 .lpm_width(2)) lpm_decode_unit (
147 .data(bus_addr[29:28]),
148 .eq(bus_ssel));
149
150
151 control control_unit (
152 .clock(sys_clock),
153 .rx_empty(usb_rx_empty),
154 .tx_full(usb_tx_full),
155 .rx_data(usb_rx_data),
156 .rx_rdreq(usb_rx_rdreq),
157 .tx_wrreq(usb_tx_wrreq),
158 .tx_data(usb_tx_data),
159 .bus_wren(bus_wren),
160 .bus_addr(bus_addr),
161 .bus_mosi(bus_mosi),
162 .bus_miso(mrg_bus_miso),
163 .bus_busy(mrg_bus_busy),
164 .led(LED));
165
166endmodule
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