source: trunk/3DEES/main.v

Last change on this file was 192, checked in by demin, 10 years ago

rename 3DEES.v to main.v
File size: 10.0 KB
Line 
1module main
2 (
3 input wire CLK_100MHz,
4 output wire LED,
5
6 input wire ADC_DCO,
7 input wire ADC_FCO,
8 input wire [5:0] ADC_D,
9
10 output wire USB_SLRD,
11 output wire USB_SLWR,
12 input wire USB_IFCLK,
13 input wire USB_FLAGA, // EMPTY flag for EP6
14 input wire USB_FLAGB, // FULL flag for EP8
15 output wire USB_PA2,
16 output wire USB_PA4,
17 output wire USB_PA6,
18 inout wire [7:0] USB_PB,
19
20 output wire RAM_CLK,
21 output wire RAM_WE,
22 output wire [21:0] RAM_ADDR,
23 inout wire RAM_DQAP,
24 inout wire [7:0] RAM_DQA,
25 inout wire RAM_DQBP,
26 inout wire [7:0] RAM_DQB
27 );
28
29 localparam N = 6;
30
31 // Turn output ports off
32/*
33 assign RAM_CLK = 1'b0;
34 assign RAM_CE1 = 1'b0;
35 assign RAM_WE = 1'b0;
36 assign RAM_ADDR = 20'h00000;
37*/
38
39 assign RAM_CLK = sys_clock;
40
41 assign USB_PA2 = ~usb_rden;
42 assign USB_PA4 = usb_addr;
43 assign USB_PA6 = ~usb_pktend;
44
45 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
46 wire usb_tx_wrreq, usb_rx_rdreq;
47 wire usb_tx_full, usb_rx_empty;
48 wire [7:0] usb_tx_data, usb_rx_data;
49 wire usb_addr;
50
51 assign USB_SLRD = ~usb_rdreq;
52 assign USB_SLWR = ~usb_wrreq;
53
54 usb_fifo usb_unit
55 (
56 .usb_clock(USB_IFCLK),
57 .usb_data(USB_PB),
58 .usb_full(~USB_FLAGB),
59 .usb_empty(~USB_FLAGA),
60 .usb_wrreq(usb_wrreq),
61 .usb_rdreq(usb_rdreq),
62 .usb_rden(usb_rden),
63 .usb_pktend(usb_pktend),
64 .usb_addr(usb_addr),
65
66 .clock(sys_clock),
67
68 .tx_full(usb_tx_full),
69 .tx_wrreq(usb_tx_wrreq),
70 .tx_data(usb_tx_data),
71
72 .rx_empty(usb_rx_empty),
73 .rx_rdreq(usb_rx_rdreq),
74 .rx_q(usb_rx_data)
75 );
76
77/*
78 reg [31:0] led_counter;
79 always @(posedge CLK_50MHz)
80 begin
81 led_counter = led_counter + 32'd1;
82 end
83 assign LED = led_counter[28];
84*/
85 wire [11:0] osc_mux_data [4:0];
86
87 wire [11:0] trg_mux_data;
88 wire trg_flag;
89
90 wire [6*12-1:0] int_mux_data [N-1:0];
91
92 wire [1:0] amp_flag [3*N-1:0];
93 wire [12:0] amp_data [3*N-1:0];
94
95 wire cls_flag;
96 wire [6:0] cls_data;
97
98 wire [1:0] amp_mux_flag [2:0];
99 wire [11:0] amp_mux_data [2:0];
100
101 wire cnt_good [3:0];
102 wire [15:0] cnt_bits_wire;
103
104 wire sys_clock, sys_frame;
105
106 wire [11:0] adc_data [N-1:0];
107 wire [11:0] sys_data [N-1:0];
108 wire [11:0] tst_data;
109
110 wire [3:0] cmp_data;
111 wire [1:0] del_data;
112
113 wire [19:0] cic_data [N-1:0];
114
115 wire [11:0] dec_data [N-1:0];
116 wire [12:0] clp_data [N-1:0];
117 wire [11:0] tmp_data;
118
119
120 wire i2c_reset;
121
122 assign tmp_data = 12'd0;
123/*
124 assign sys_clock = CLK_100MHz;
125*/
126 sys_pll sys_pll_unit(
127 .inclk0(CLK_100MHz),
128 .c0(sys_clock));
129
130/*
131 sys_pll sys_pll_unit(
132 .inclk0(CLK_100MHz),
133 .c0(sys_clock),
134 .c1(ADC_DCO),
135 .c2(ADC_FCO));
136
137 wire ADC_DCO, ADC_FCO;
138
139
140 test test_unit(
141 .clock(ADC_FCO),
142 .data(tst_data));
143*/
144
145 adc_lvds #(
146 .size(6),
147 .width(12)) adc_lvds_unit (
148 .clock(sys_clock),
149 .lvds_dco(ADC_DCO),
150 .lvds_fco(ADC_FCO),
151 .lvds_d(ADC_D),
152// .test(tst_data),
153 .adc_frame(sys_frame),
154 .adc_data({
155 adc_data[5], adc_data[3], adc_data[4], // D3, D1, D2
156 adc_data[2], adc_data[1], adc_data[0]})); // S2, S1_S, S1_F
157
158 wire [15:0] cfg_bits [63:0];
159 wire [1023:0] int_cfg_bits;
160
161 wire [39:0] cfg_mux_selector;
162
163 wire cfg_reset;
164
165 wire [2:0] bus_ssel;
166 wire bus_wren;
167 wire [31:0] bus_addr;
168 wire [15:0] bus_mosi;
169 wire [15:0] bus_miso [2:0];
170 wire [2:0] bus_busy;
171
172 wire [15:0] mrg_bus_miso;
173 wire mrg_bus_busy;
174
175 wire [3*16-1:0] int_bus_miso;
176
177 genvar j;
178
179 generate
180 for (j = 0; j < 64; j = j + 1)
181 begin : CONFIGURATION_OUTPUT
182 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
183 end
184 endgenerate
185
186 configuration configuration_unit (
187 .clock(sys_clock),
188 .reset(cfg_reset),
189 .bus_ssel(bus_ssel[0]),
190 .bus_wren(bus_wren),
191 .bus_addr(bus_addr[5:0]),
192 .bus_mosi(bus_mosi),
193 .bus_miso(bus_miso[0]),
194 .bus_busy(bus_busy[0]),
195 .cfg_bits(int_cfg_bits));
196
197 generate
198 for (j = 0; j < 6; j = j + 1)
199 begin : MUX_DATA
200 assign int_mux_data[j] = {
201 {4'd0, cls_flag, 7'd0},
202 {5'd0, cls_data},
203 {4'd0, amp_flag[j][0], 7'd0},
204 amp_data[j][11:0],
205 clp_data[j][11:0],
206 sys_data[j]
207 };
208 end
209 endgenerate
210
211 assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
212
213 lpm_mux #(
214 .lpm_size(6*6),
215 .lpm_type("LPM_MUX"),
216 .lpm_width(12),
217 .lpm_widths(6)) trg_mux_unit (
218 .sel(cfg_bits[4][13:8]),
219 .data({
220 int_mux_data[5], int_mux_data[4], int_mux_data[3],
221 int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
222 .result(trg_mux_data));
223
224 generate
225 for (j = 0; j < 5; j = j + 1)
226 begin : OSC_CHAIN
227
228 lpm_mux #(
229 .lpm_size(6*6),
230 .lpm_type("LPM_MUX"),
231 .lpm_width(12),
232 .lpm_widths(6)) osc_mux_unit (
233 .sel(cfg_mux_selector[j*8+5:j*8]),
234 .data({
235 int_mux_data[5], int_mux_data[4], int_mux_data[3],
236 int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
237 .result(osc_mux_data[j]));
238 end
239 endgenerate
240
241 trigger trigger_unit (
242 .clock(sys_clock),
243 .frame(sys_frame),
244 .reset(cfg_bits[0][0]),
245 .cfg_data(cfg_bits[5][11:0]),
246 .trg_data(trg_mux_data),
247 .trg_flag(trg_flag));
248
249 oscilloscope oscilloscope_unit (
250 .clock(sys_clock),
251 .frame(sys_frame),
252 .reset(cfg_bits[0][1]),
253 .cfg_data(cfg_bits[5][12]),
254 .trg_flag(trg_flag),
255 .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
256 .ram_wren(RAM_WE),
257 .ram_addr(RAM_ADDR),
258 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
259 .bus_ssel(bus_ssel[1]),
260 .bus_wren(bus_wren),
261 .bus_addr(bus_addr[19:0]),
262 .bus_mosi(bus_mosi),
263 .bus_miso(bus_miso[1]),
264 .bus_busy(bus_busy[1]));
265
266 filter #(.size(6), .width(12)) filter_unit (
267 .clock(sys_clock),
268 .frame(sys_frame),
269 .reset(1'b0),
270 .inp_data({sys_data[5], sys_data[4], sys_data[3],
271 sys_data[2], sys_data[1], sys_data[0]}),
272 .out_data({cic_data[5], cic_data[4], cic_data[3],
273 cic_data[2], cic_data[1], cic_data[0]}));
274/*
275 new_filter #(.size(6), .width(12)) filter_unit (
276 .clock(sys_clock),
277 .frame(sys_frame),
278 .reset(1'b0),
279 .inp_data({sys_data[5], sys_data[4], sys_data[3],
280 sys_data[2], sys_data[1], sys_data[0]}),
281 .out_data({cic_data[5], cic_data[4], cic_data[3],
282 cic_data[2], cic_data[1], cic_data[0]}));
283*/
284
285 generate
286 for (j = 0; j < 2; j = j + 1)
287 begin : DECONV_CHAIN
288
289 clip #(.shift(21), .width(19), .widthr(13)) clip_unit (
290 .clock(sys_clock),
291 .frame(sys_frame),
292 .reset(1'b0),
293// .del_data({6'd0, 6'd32, 6'd32, 6'd32}),
294 .del_data({6'd0, cfg_bits[43+6*j][5:0], cfg_bits[41+6*j][5:0], cfg_bits[39+6*j][5:0]}),
295 .amp_data({6'd0, 6'd20, 6'd20, 6'd20}),
296// .tau_data({16'd0, 16'd19835, 16'd19835, 16'd19835}),
297// exp(-32/1000)*1024*20
298 .tau_data({16'd0, cfg_bits[42+6*j], cfg_bits[40+6*j], cfg_bits[38+6*j]}),
299 .inp_data({
300 19'd0, cic_data[j*3+2][18:0], cic_data[j*3+1][18:0], cic_data[j*3+0][18:0]}),
301 .out_data({
302 tmp_data, clp_data[j*3+2], clp_data[j*3+1], clp_data[j*3+0]}));
303
304 end
305 endgenerate
306
307 generate
308 for (j = 0; j < 6; j = j + 1)
309 begin : MCA_CHAIN
310/*
311 shift #(.shift(11), .width(19), .widthr(13)) shift_unit (
312 .clock(sys_clock),
313 .frame(sys_frame),
314 .reset(1'b0),
315 .amp_data(6'd21),
316 .inp_data(cic_data[j][18:0]),
317 .out_data(clp_data[j]));
318*/
319 assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
320
321 amplitude #(.width(13)) amplitude_unit (
322 .clock(sys_clock),
323 .frame(sys_frame),
324 .reset(1'b0),
325// .min_data(13'd20),
326 .min_data(cfg_bits[10+j][12:0]),
327 .max_data(13'd4095),
328 .inp_data(clp_data[j]),
329 .out_flag(amp_flag[j]),
330 .out_data(amp_data[j]));
331 end
332 endgenerate
333
334// {D3, D2, D1, S2, S1_S, S1_F}
335 classifier #(.width(12)) classifier_unit (
336 .clock(sys_clock),
337 .frame(sys_frame),
338 .reset(1'b0),
339// .cfg_data({12'd20, 12'd20,
340// 12'd20, 12'd20, 12'd20, 12'd20, 12'd2000, 12'd20,
341// 12'd20, 12'd2000, 12'd2000, 12'd20, 12'd1000, 12'd1000}),
342 .cfg_data({cfg_bits[37][11:0], cfg_bits[36][11:0],
343 cfg_bits[35][11:0], cfg_bits[34][11:0], cfg_bits[33][11:0], cfg_bits[32][11:0],
344 cfg_bits[31][11:0], cfg_bits[30][11:0], cfg_bits[29][11:0], cfg_bits[28][11:0],
345 cfg_bits[27][11:0], cfg_bits[26][11:0], cfg_bits[25][11:0], cfg_bits[24][11:0],
346 cfg_bits[23][11:0], cfg_bits[22][11:0], cfg_bits[21][11:0], cfg_bits[20][11:0],
347 cfg_bits[19][11:0], cfg_bits[18][11:0], cfg_bits[17][11:0], cfg_bits[16][11:0]}),
348 .inp_data({amp_data[5][11:0], amp_data[4][11:0], amp_data[3][11:0],
349 amp_data[2][11:0], amp_data[1][11:0], amp_data[0][11:0]}),
350 .inp_flag({amp_flag[5][0], amp_flag[4][0], amp_flag[3][0],
351 amp_flag[2][0], amp_flag[1][0], amp_flag[0][0]}),
352 .out_flag(cls_flag),
353 .out_data(cls_data));
354
355 histogram32 histogram32_unit (
356 .clock(sys_clock),
357 .frame(sys_frame),
358 .reset(cfg_bits[0][5]),
359 .hst_good(cls_flag & cfg_bits[6][0]),
360 .hst_data(cls_data),
361 .bus_ssel(bus_ssel[2]),
362 .bus_wren(bus_wren),
363 .bus_addr(bus_addr[7:0]),
364 .bus_mosi(bus_mosi),
365 .bus_miso(bus_miso[2]),
366 .bus_busy(bus_busy[2]));
367
368
369 generate
370 for (j = 0; j < 3; j = j + 1)
371 begin : BUS_OUTPUT
372 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
373 end
374 endgenerate
375
376 lpm_mux #(
377 .lpm_size(3),
378 .lpm_type("LPM_MUX"),
379 .lpm_width(16),
380 .lpm_widths(2)) bus_miso_mux_unit (
381 .sel(bus_addr[29:28]),
382 .data(int_bus_miso),
383 .result(mrg_bus_miso));
384
385 lpm_mux #(
386 .lpm_size(3),
387 .lpm_type("LPM_MUX"),
388 .lpm_width(1),
389 .lpm_widths(2)) bus_busy_mux_unit (
390 .sel(bus_addr[29:28]),
391 .data(bus_busy),
392 .result(mrg_bus_busy));
393
394 lpm_decode #(
395 .lpm_decodes(3),
396 .lpm_type("LPM_DECODE"),
397 .lpm_width(2)) lpm_decode_unit (
398 .data(bus_addr[29:28]),
399 .eq(bus_ssel));
400
401
402 control control_unit (
403 .clock(sys_clock),
404 .rx_empty(usb_rx_empty),
405 .tx_full(usb_tx_full),
406 .rx_data(usb_rx_data),
407 .rx_rdreq(usb_rx_rdreq),
408 .tx_wrreq(usb_tx_wrreq),
409 .tx_data(usb_tx_data),
410 .bus_wren(bus_wren),
411 .bus_addr(bus_addr),
412 .bus_mosi(bus_mosi),
413 .bus_miso(mrg_bus_miso),
414 .bus_busy(mrg_bus_busy),
415 .led(LED));
416
417/*
418 altserial_flash_loader #(
419 .enable_shared_access("OFF"),
420 .enhanced_mode(1),
421 .intended_device_family("Cyclone III")) sfl_unit (
422 .noe(1'b0),
423 .asmi_access_granted(),
424 .asmi_access_request(),
425 .data0out(),
426 .dclkin(),
427 .scein(),
428 .sdoin());
429*/
430
431endmodule
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