source: trunk/3DEES/delay.v@ 178

Last change on this file since 178 was 107, checked in by demin, 14 years ago

Starting to test signal shaping algorithms

File size: 653 bytes
Line 
1module delay
2 #(
3 parameter width = 12,
4 parameter length = 32
5 )
6 (
7 input wire clock, frame, reset,
8 input wire [width-1:0] inp_data,
9 output wire [width-1:0] out_data
10 );
11
12 reg [width-1:0] int_pipe_reg [length-1:0];
13
14 integer i;
15
16 always @(posedge clock)
17 begin
18 if (reset)
19 begin
20 for(i = 0; i < length; i = i + 1)
21 begin
22 int_pipe_reg[i] <= 0;
23 end
24 end
25 else if (frame)
26 begin
27 for(i = 0; i <= 30; i = i + 1)
28 begin
29 int_pipe_reg[i+1] <= int_pipe_reg[i];
30 end
31 int_pipe_reg[0] <= inp_data;
32 end
33 end
34
35 assign out_data = int_pipe_reg[length-1];
36
37endmodule
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