module classifier
	#(
		parameter	width	=	12 // bit width of the input data (unsigned)
	)
	(
		input	wire					clock, frame, reset,
		input	wire	[14*width-1:0]	cfg_data,
		input	wire	[6*width-1:0]	inp_data, // {D3, D2, D1, S2, S1_S, S1_F}
		input	wire	[5:0]			inp_flag,
		output	wire	[5:0]			out_data,
		output	wire					out_flag
	);

	reg					int_case_reg, int_case_next;
	reg					out_flag_reg, out_flag_next;
	reg		[5:0]		out_data_reg, out_data_next;
	reg		[width-1:0]	inp_data_reg [5:0], inp_data_next [5:0];
	reg		[15:0]		int_pipe_reg [19:0], int_pipe_next [19:0];	
	reg		[1:0]		int_data_reg [3:0], int_data_next [3:0];

	wire	[width-1:0]	inp_data_wire [5:0];
	wire	[3:0]		int_pipe_wire [5:0];
	wire	[13:0]		int_comp_wire;

	integer i;
	genvar j;

	generate
		for (j = 0; j < 6; j = j + 1)
		begin : CLASSIFIER_INPUT_DATA
			assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
		end
	endgenerate

	generate
		assign int_comp_wire[0] = (inp_data_reg[0] > cfg_data[width-1:0]);
		assign int_comp_wire[1] = (inp_data_reg[1] > cfg_data[2*width-1:width]);
		for (j = 0; j < 4; j = j + 1)
		begin : CLASSIFIER_COMPARTORS
			assign int_comp_wire[j*3+0+2] = (inp_data_reg[j+2] > cfg_data[(j*3+0+2)*width+width-1:(j*3+0+2)*width]);
			assign int_comp_wire[j*3+1+2] = (inp_data_reg[j+2] > cfg_data[(j*3+1+2)*width+width-1:(j*3+1+2)*width]);
			assign int_comp_wire[j*3+2+2] = (inp_data_reg[j+2] > cfg_data[(j*3+2+2)*width+width-1:(j*3+2+2)*width]);
		end                                                                                        
	endgenerate
				
	generate
		for (j = 0; j < 4; j = j + 1)
		begin : CLASSIFIER_PIPELINE
		    assign int_pipe_wire[0][j] = (|int_pipe_reg[j]);
		    assign int_pipe_wire[1][j] = (|int_pipe_reg[j+4]);
			assign int_pipe_wire[j+2][0] = (|int_pipe_reg[j*3+0+8]);
			assign int_pipe_wire[j+2][1] = (|int_pipe_reg[j*3+1+8]);
			assign int_pipe_wire[j+2][2] = (|int_pipe_reg[j*3+2+8]);
			assign int_pipe_wire[j+2][3] = 1'b0;
		end
	endgenerate
		
	always @(posedge clock)
	begin
		if (reset)
		begin
			out_data_reg <= {(6){1'b0}};
			out_flag_reg <= 1'b0;
			for (i = 0; i < 6; i = i + 1)
			begin
				inp_data_reg[i] <= {(width){1'b0}};
			end
			for (i = 0; i < 20; i = i + 1)
			begin
				int_pipe_reg[i] <= {(16){1'b0}};
			end
			for (i = 0; i < 4; i = i + 1)
			begin
				int_data_reg[i] <= {(2){1'b0}};
			end
		end
		else
		begin
			out_data_reg <= out_data_next;
			out_flag_reg <= out_flag_next;
			for (i = 0; i < 6; i = i + 1)
			begin
				inp_data_reg[i] <= inp_data_next[i];
			end
			for (i = 0; i < 20; i = i + 1)
			begin
				int_pipe_reg[i] <= int_pipe_next[i];
			end
			for (i = 0; i < 4; i = i + 1)
			begin
				int_data_reg[i] <= int_data_next[i];
			end
		end
	end
	
	always @*
	begin
		out_data_next = out_data_reg;
		out_flag_next = out_flag_reg;
		for (i = 0; i < 6; i = i + 1)
		begin
			inp_data_next[i] = inp_data_reg[i];
		end
		for (i = 0; i < 20; i = i + 1)
		begin
			int_pipe_next[i] = int_pipe_reg[i];
		end
		for (i = 0; i < 4; i = i + 1)
		begin
			int_data_next[i] = int_data_reg[i];
		end

		if (frame)
		begin
			for (i = 0; i < 6; i = i + 1)
			begin
				inp_data_next[i] = inp_flag[i] ? inp_data_wire[i] : {(width){1'b0}};
			end
		
			if (out_flag_reg)
			begin
				out_flag_next = 1'b0;
				for (i = 0; i < 20; i = i + 1)
				begin
					int_pipe_next[i] = {(16){1'b0}};
				end
				out_data_next = {(6){1'b0}};
			end
			else
			begin
				out_flag_next = 1'b1;
				int_pipe_next[0] = {int_pipe_reg[0][14:0], int_comp_wire[0]};
				int_pipe_next[1] = {int_pipe_reg[1][14:0], int_comp_wire[1]};
				for (i = 2; i < 8; i = i + 1)
				begin
					int_pipe_next[i] = {int_pipe_reg[i][14:0], inp_flag[i-2]};
				end
				for (i = 8; i < 20; i = i + 1)
				begin
					int_pipe_next[i] = {int_pipe_reg[i][14:0], int_comp_wire[i-6]};
				end

				for (i = 0; i < 4; i = i + 1)
				begin
					case (int_pipe_wire[i+2][2:0])
						3'b000: int_data_next[i] = 2'd0;
						3'b001: int_data_next[i] = 2'd1;
						3'b011: int_data_next[i] = 2'd2;
						3'b111: int_data_next[i] = 2'd3;
						default: int_data_next[i] = 2'd0;
					endcase
				end

				case ({int_pipe_wire[1], int_pipe_wire[0][3]^int_pipe_wire[0][2]})
					5'b00011: out_data_next[3:0] = {2'd0, int_data_next[0]};
					5'b00111: out_data_next[3:0] = {2'd1, int_data_next[1]};
					5'b01111: out_data_next[3:0] = {2'd2, int_data_next[2]};
					5'b11111: out_data_next[3:0] = {2'd3, int_data_next[3]};
					default: out_flag_next = 1'b0;
				endcase
	
				case (int_pipe_wire[0])
					// S1_F, electron
					4'b0001: out_data_next[5:4] = 2'd0;
										
					// S1_F, proton
					4'b0101: out_data_next[5:4] = 2'd1;
										 
					// S1_S, electron
					4'b0010: out_data_next[5:4] = 2'd2;
										 
					// S1_S, proton
					4'b1010: out_data_next[5:4] = 2'd3;
										 
					default: out_flag_next = 1'b0;
				endcase
			end
		end
	end

//	assign out_data = {2'd0, int_data_reg[1]};
//	assign out_data = {2'd0, int_pipe_wire[7:4]};
	assign out_data = out_data_reg;
	assign out_flag = out_flag_reg;

endmodule