| 1 | module usb_fifo
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| 2 | (
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| 3 | input wire usb_clock,
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| 4 | inout wire [7:0] usb_data,
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| 5 | input wire usb_full, usb_empty,
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| 6 | output wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend,
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| 7 | output wire usb_addr,
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| 8 |
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| 9 | input wire clock,
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| 10 | input wire tx_wrreq, rx_rdreq,
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| 11 | input wire [7:0] tx_data,
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| 12 | output wire tx_full, rx_empty,
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| 13 | output wire [7:0] rx_q
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| 14 | );
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| 15 |
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| 16 | wire int_rx_full, int_tx_empty;
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| 17 | wire rx_ready, tx_ready;
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| 18 | wire int_rdreq, int_wrreq, int_pktend;
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| 19 | reg is_rx_addr_ok;
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| 20 | reg [8:0] byte_counter;
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| 21 | reg [4:0] idle_counter;
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| 22 |
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| 23 | wire [7:0] int_rx_data = usb_data;
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| 24 | wire [7:0] int_tx_q;
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| 25 |
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| 26 | dcfifo #(
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| 27 | .intended_device_family("Cyclone III"),
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| 28 | .lpm_numwords(16),
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| 29 | .lpm_showahead("ON"),
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| 30 | .lpm_type("dcfifo"),
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| 31 | .lpm_width(8),
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| 32 | .lpm_widthu(4),
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| 33 | .rdsync_delaypipe(4),
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| 34 | .wrsync_delaypipe(4),
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| 35 | .overflow_checking("ON"),
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| 36 | .underflow_checking("ON"),
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| 37 | .use_eab("OFF"),
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| 38 | .write_aclr_synch("OFF")) fifo_tx (
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| 39 | .aclr(1'b0),
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| 40 | .data(tx_data),
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| 41 | .rdclk(usb_clock),
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| 42 | .rdreq(int_wrreq),
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| 43 | .wrclk(clock),
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| 44 | .wrreq(tx_wrreq),
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| 45 | .q(int_tx_q),
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| 46 | .rdempty(int_tx_empty),
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| 47 | .wrfull(tx_full),
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| 48 | .rdfull(),
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| 49 | .rdusedw(),
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| 50 | .wrempty(),
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| 51 | .wrusedw());
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| 52 |
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| 53 | dcfifo #(
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| 54 | .intended_device_family("Cyclone III"),
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| 55 | .lpm_numwords(16),
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| 56 | .lpm_showahead("ON"),
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| 57 | .lpm_type("dcfifo"),
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| 58 | .lpm_width(8),
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| 59 | .lpm_widthu(4),
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| 60 | .rdsync_delaypipe(4),
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| 61 | .wrsync_delaypipe(4),
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| 62 | .overflow_checking("ON"),
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| 63 | .underflow_checking("ON"),
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| 64 | .use_eab("OFF"),
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| 65 | .write_aclr_synch("OFF")) fifo_rx (
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| 66 | .aclr(1'b0),
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| 67 | .data(int_rx_data),
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| 68 | .rdclk(clock),
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| 69 | .rdreq(rx_rdreq),
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| 70 | .wrclk(usb_clock),
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| 71 | .wrreq(int_rdreq),
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| 72 | .q(rx_q),
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| 73 | .rdempty(rx_empty),
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| 74 | .wrfull(int_rx_full),
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| 75 | .rdfull(),
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| 76 | .rdusedw(),
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| 77 | .wrempty(),
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| 78 | .wrusedw());
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| 79 |
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| 80 | assign rx_ready = (~usb_empty) & (~int_rx_full) & (~int_pktend);
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| 81 | assign tx_ready = (~rx_ready) & (~usb_full) & (~int_tx_empty) & (~int_pktend);
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| 82 |
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| 83 | assign int_rdreq = (rx_ready) & (is_rx_addr_ok);
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| 84 | assign int_wrreq = (tx_ready) & (~is_rx_addr_ok);
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| 85 |
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| 86 | assign int_pktend = (&idle_counter);
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| 87 |
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| 88 | always @ (posedge usb_clock)
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| 89 | begin
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| 90 | // respect 1 clock delay between fifo selection
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| 91 | // and data transfer operations
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| 92 | is_rx_addr_ok <= rx_ready;
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| 93 |
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| 94 | // assert pktend if buffer contains unsent data
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| 95 | // and fifo_tx_unit stays empty for more than 30 clocks
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| 96 | if (int_pktend)
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| 97 | begin
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| 98 | byte_counter <= 9'd0;
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| 99 | idle_counter <= 5'd0;
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| 100 | end
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| 101 | else if (int_wrreq)
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| 102 | begin
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| 103 | byte_counter <= byte_counter + 9'd1;
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| 104 | idle_counter <= 5'd0;
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| 105 | end
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| 106 | else if ((|byte_counter) & (int_tx_empty) & (~rx_ready))
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| 107 | begin
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| 108 | byte_counter <= byte_counter;
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| 109 | idle_counter <= idle_counter + 5'd1;
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| 110 | end
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| 111 |
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| 112 | end
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| 113 |
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| 114 | assign usb_pktend = int_pktend;
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| 115 | assign usb_rdreq = int_rdreq;
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| 116 | assign usb_wrreq = int_wrreq;
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| 117 | assign usb_rden = int_rdreq;
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| 118 | assign usb_addr = rx_ready;
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| 119 | assign usb_data = int_wrreq ? int_tx_q : 8'bz;
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| 120 |
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| 121 | endmodule
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