source: sandbox/MultiChannelUSB/spi_fifo.v@ 120

Last change on this file since 120 was 107, checked in by demin, 14 years ago

Starting to test signal shaping algorithms

File size: 2.2 KB
Line 
1module spi_fifo
2 (
3 input wire clock, reset,
4
5 input wire bus_ssel, bus_wren,
6 input wire [15:0] bus_mosi,
7
8 output wire bus_busy,
9
10 output wire spi_sel,
11 output wire spi_sdo,
12 output wire spi_clk
13 );
14
15 wire int_rdempty, int_wrfull;
16 wire [15:0] int_q;
17
18 reg int_bus_busy;
19 reg int_rdreq, int_wrreq;
20 reg int_clken, int_sdo, int_sel;
21 reg [15:0] int_bus_mosi;
22 reg [15:0] int_data;
23 reg [2:0] clk_cntr;
24 reg [3:0] bit_cntr;
25 reg [1:0] state;
26
27 scfifo #(
28 .add_ram_output_register("OFF"),
29 .intended_device_family("Cyclone III"),
30 .lpm_numwords(16),
31 .lpm_showahead("ON"),
32 .lpm_type("scfifo"),
33 .lpm_width(16),
34 .lpm_widthu(4),
35 .overflow_checking("ON"),
36 .underflow_checking("ON"),
37 .use_eab("OFF")) fifo_tx (
38 .rdreq((~int_rdempty) & (int_rdreq) & (&clk_cntr)),
39 .aclr(1'b0),
40 .clock(clock),
41 .wrreq(int_wrreq),
42 .data(int_bus_mosi),
43 .empty(int_rdempty),
44 .q(int_q),
45 .full(int_wrfull),
46 .almost_empty(),
47 .almost_full(),
48 .sclr(),
49 .usedw());
50
51 always @ (posedge clock)
52 begin
53 int_bus_busy <= int_wrfull;
54
55 if (bus_ssel)
56 begin
57 if (~int_wrfull & bus_wren)
58 begin
59 int_bus_mosi <= bus_mosi;
60 int_wrreq <= 1'b1;
61 end
62 end
63
64 if (~int_wrfull & int_wrreq)
65 begin
66 int_wrreq <= 1'b0;
67 end
68
69 end
70
71 always @ (posedge clock)
72 begin
73 clk_cntr <= clk_cntr + 3'd1;
74 if (&clk_cntr)
75 begin
76 case (state)
77 0:
78 begin
79 int_sdo <= 1'b0;
80 int_sel <= 1'b1;
81 int_clken <= 1'b0;
82 int_rdreq <= 1'b1;
83 state <= 2'd1;
84 end
85
86 1:
87 begin
88 if (~int_rdempty)
89 begin
90 int_rdreq <= 1'b0;
91 int_data <= int_q;
92 bit_cntr <= 4'd0;
93 state <= 2'd2;
94 end
95 end
96
97
98 2:
99 begin // data
100 int_clken <= 1'b1;
101 int_sel <= 1'b0;
102 int_sdo <= int_data[11];
103 int_data <= {int_data[10:0], 1'b0};
104 bit_cntr <= bit_cntr + 4'd1;
105 if (bit_cntr == 4'd11)
106 begin
107 state <= 2'd3;
108 end
109 end
110
111 3:
112 begin
113 int_sdo <= 1'b0;
114 int_clken <= 1'b0;
115 state <= 2'd0;
116 end
117
118 endcase
119 end
120 end
121
122 // output logic
123 assign bus_busy = int_bus_busy;
124 assign spi_clk = (int_clken ? clk_cntr[2] : 1'b1);
125 assign spi_sdo = int_sdo;
126 assign spi_sel = int_sel;
127
128endmodule
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