source: sandbox/MultiChannelUSB/oscilloscope.v@ 131

Last change on this file since 131 was 103, checked in by demin, 15 years ago

add fourth oscilloscope channel
File size: 5.4 KB
Line 
1module oscilloscope
2 (
3 input wire clock, frame, reset,
4
5 input wire cfg_data,
6
7 input wire trg_flag,
8
9 input wire [63:0] osc_data,
10
11 output wire ram_wren,
12 output wire [19:0] ram_addr,
13 inout wire [17:0] ram_data,
14
15 input wire bus_ssel, bus_wren,
16 input wire [19:0] bus_addr,
17 input wire [15:0] bus_mosi,
18
19 output wire [15:0] bus_miso,
20 output wire bus_busy
21 );
22
23
24 reg [63:0] osc_data_reg, osc_data_next;
25
26 reg [2:0] int_case_reg, int_case_next;
27
28 reg int_trig_reg, int_trig_next;
29 reg [19:0] int_trig_addr_reg, int_trig_addr_next;
30
31 reg [19:0] int_cntr_reg [1:0];
32 reg [19:0] int_cntr_next [1:0];
33
34 reg [15:0] bus_miso_reg, bus_miso_next;
35 reg bus_busy_reg, bus_busy_next;
36
37 reg ram_wren_reg [2:0];
38 reg ram_wren_next [2:0];
39
40 reg [17:0] ram_data_reg [2:0];
41 reg [17:0] ram_data_next [2:0];
42
43 reg [19:0] ram_addr_reg, ram_addr_next;
44
45 wire [17:0] ram_wren_wire;
46
47 assign ram_wren = ~ram_wren_reg[0];
48 assign ram_addr = ram_addr_reg;
49
50 integer i;
51 genvar j;
52
53 generate
54 for (j = 0; j < 18; j = j + 1)
55 begin : SRAM_WREN
56 assign ram_wren_wire[j] = ram_wren_reg[2];
57 assign ram_data[j] = ram_wren_wire[j] ? ram_data_reg[2][j] : 1'bz;
58 end
59 endgenerate
60
61 always @(posedge clock)
62 begin
63 if (reset)
64 begin
65 osc_data_reg <= 64'd0;
66 ram_addr_reg <= 20'd0;
67 bus_miso_reg <= 16'd0;
68 bus_busy_reg <= 1'b0;
69 int_case_reg <= 5'd0;
70 int_cntr_reg[0] <= 20'd0;
71 int_cntr_reg[1] <= 20'd0;
72 int_trig_reg <= 1'b0;
73 int_trig_addr_reg <= 20'd0;
74
75 for(i = 0; i <= 2; i = i + 1)
76 begin
77 ram_wren_reg[i] <= 1'b0;
78 ram_data_reg[i] <= 16'd0;
79 end
80 end
81 else
82 begin
83 osc_data_reg <= osc_data_next;
84 ram_addr_reg <= ram_addr_next;
85 bus_miso_reg <= bus_miso_next;
86 bus_busy_reg <= bus_busy_next;
87 int_case_reg <= int_case_next;
88 int_cntr_reg[0] <= int_cntr_next[0];
89 int_cntr_reg[1] <= int_cntr_next[1];
90 int_trig_reg <= int_trig_next;
91 int_trig_addr_reg <= int_trig_addr_next;
92
93 for(i = 0; i <= 2; i = i + 1)
94 begin
95 ram_wren_reg[i] <= ram_wren_next[i];
96 ram_data_reg[i] <= ram_data_next[i];
97 end
98 end
99 end
100
101 always @*
102 begin
103
104 osc_data_next = osc_data_reg;
105 ram_addr_next = ram_addr_reg;
106 bus_miso_next = bus_miso_reg;
107 bus_busy_next = bus_busy_reg;
108 int_case_next = int_case_reg;
109 int_cntr_next[0] = int_cntr_reg[0];
110 int_cntr_next[1] = int_cntr_reg[1];
111 int_trig_next = int_trig_reg;
112 int_trig_addr_next = int_trig_addr_reg;
113
114 for(i = 0; i < 2; i = i + 1)
115 begin
116 ram_wren_next[i+1] = ram_wren_reg[i];
117 ram_data_next[i+1] = ram_data_reg[i];
118 end
119 ram_wren_next[0] = 1'b0;
120 ram_data_next[0] = 18'd0;
121
122 case (int_case_reg)
123 0:
124 begin
125 bus_busy_next = 1'b0;
126 int_cntr_next[0] = 20'd0;
127 int_cntr_next[1] = 20'd0;
128 int_trig_next = 1'b0;
129
130 if (bus_ssel)
131 begin
132 bus_miso_next = {ram_data[17:10], ram_data[8:1]};
133 ram_wren_next[0] = bus_wren;
134 if (bus_wren)
135 begin
136 ram_addr_next = bus_addr;
137 ram_data_next[0] = {bus_mosi[15:8], 1'b0, bus_mosi[7:0], 1'b0};
138 end
139 else
140 begin
141 ram_addr_next = int_trig_addr_reg + bus_addr;
142// ram_addr_next = bus_addr;
143 end
144 end
145 else if (cfg_data)
146 begin
147 // start recording
148 ram_wren_next[0] = 1'b1;
149 ram_data_next[0] = 18'd0;
150 ram_addr_next = 20'd0;
151 bus_busy_next = 1'b1;
152 int_case_next = 3'd1;
153 int_trig_addr_next = 20'd0;
154// int_cntr_next[0] = {cfg_data[7:0], 10'd0};
155 int_cntr_next[0] = 20'd262143;
156// int_cntr_next[1] = {cfg_data[15:8], 10'd0};
157 int_cntr_next[1] = 20'd5000;
158 end
159
160 end
161
162 // write zeros
163 1:
164 begin
165 ram_wren_next[0] = 1'b1;
166 ram_data_next[0] = 18'd2;
167 if(&ram_addr_reg)
168 begin
169 int_case_next = 3'd2;
170 end
171 else
172 begin
173 ram_addr_next = ram_addr_reg + 20'd1;
174 end
175 end
176
177 // sample recording
178 2:
179 begin
180 if (frame)
181 begin
182 osc_data_next = osc_data;
183 ram_addr_next = ram_addr_reg + 20'd1;
184 ram_wren_next[0] = 1'b1;
185 ram_data_next[0] = {osc_data[15:8], 1'b0, osc_data[7:0], 1'b0};
186
187 int_case_next = 3'd3;
188
189 if (|int_cntr_reg[1])
190 begin
191 int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
192 int_cntr_next[1] = int_cntr_reg[1] - 20'd1;
193 end
194 else if (int_trig_reg)
195 begin
196 if (|int_cntr_reg[0])
197 begin
198 int_cntr_next[0] = int_cntr_reg[0] - 20'd1;
199 end
200 end
201 else if (trg_flag)
202 begin
203 int_trig_next = 1'b1;
204 int_trig_addr_next = ram_addr_reg - 20'd19999;
205 end
206 end
207 end
208
209 3:
210 begin
211 ram_addr_next = ram_addr_reg + 20'd1;
212 ram_wren_next[0] = 1'b1;
213 ram_data_next[0] = {osc_data_reg[31:24], 1'b0, osc_data_reg[23:16], 1'b0};
214 int_case_next = 3'd4;
215 end
216
217 4:
218 begin
219 ram_addr_next = ram_addr_reg + 20'd1;
220 ram_wren_next[0] = 1'b1;
221 ram_data_next[0] = {osc_data_reg[47:40], 1'b0, osc_data_reg[39:32], 1'b0};
222 int_case_next = 3'd5;
223 end
224
225 5:
226 begin
227 ram_addr_next = ram_addr_reg + 20'd1;
228 ram_wren_next[0] = 1'b1;
229 ram_data_next[0] = {osc_data_reg[63:56], 1'b0, osc_data_reg[55:48], 1'b0};
230 if (|int_cntr_reg[0])
231 begin
232 int_case_next = 3'd2;
233 end
234 else
235 begin
236 int_case_next = 3'd0;
237 end
238 end
239
240 endcase
241 end
242
243 assign bus_miso = bus_miso_reg;
244 assign bus_busy = bus_busy_reg;
245
246endmodule
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