source: sandbox/MultiChannelUSB/filter.v@ 201

Last change on this file since 201 was 158, checked in by demin, 13 years ago

increase lfsr length
File size: 5.7 KB
Line 
1module filter
2 #(
3 parameter size = 3, // number of channels
4 parameter width = 12 // bit width of the input data (unsigned)
5 )
6 (
7 input wire clock, frame, reset,
8 input wire [size*width-1:0] inp_data,
9 output wire [size*widthr-1:0] out_data
10 );
11
12 localparam widthr = width + 8;
13 /*
14 5-bit LFSR with additional bits to keep track of previous values
15 */
16 reg [31:0] int_lfsr_reg, int_lfsr_next;
17
18 reg int_wren_reg, int_wren_next;
19 reg int_flag_reg, int_flag_next;
20 reg int_chan_reg, int_chan_next;
21 reg [1:0] int_case_reg, int_case_next;
22 reg [5:0] int_addr_reg, int_addr_next;
23
24 wire [5:0] int_addr_wire;
25
26 reg [size*widthr-1:0] acc_data_reg [1:0], acc_data_next [1:0];
27 reg [size*widthr-1:0] int_data_reg [2:0], int_data_next [2:0];
28
29 wire [size*widthr-1:0] acc_data_wire [1:0], del_data_wire;
30
31 integer i;
32 genvar j;
33
34 generate
35 for (j = 0; j < size; j = j + 1)
36 begin : INT_DATA
37 assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
38
39 assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
40 acc_data_reg[0][j*widthr+widthr-1:j*widthr]
41 - del_data_wire[j*widthr+widthr-1:j*widthr]
42 + acc_data_reg[1][j*widthr+widthr-1:j*widthr];
43
44 end
45 endgenerate
46
47 altsyncram #(
48 .address_aclr_b("NONE"),
49 .address_reg_b("CLOCK0"),
50 .clock_enable_input_a("BYPASS"),
51 .clock_enable_input_b("BYPASS"),
52 .clock_enable_output_b("BYPASS"),
53 .intended_device_family("Cyclone III"),
54 .lpm_type("altsyncram"),
55 .numwords_a(64),
56 .numwords_b(64),
57 .operation_mode("DUAL_PORT"),
58 .outdata_aclr_b("NONE"),
59 .outdata_reg_b("CLOCK0"),
60 .power_up_uninitialized("FALSE"),
61 .read_during_write_mode_mixed_ports("DONT_CARE"),
62 .widthad_a(6),
63 .widthad_b(6),
64 .width_a(size*widthr),
65 .width_b(size*widthr),
66 .width_byteena_a(1)) ram_unit_1 (
67 .wren_a(int_wren_reg),
68 .clock0(clock),
69 .address_a(int_addr_reg),
70 .address_b(int_addr_wire),
71 .data_a(acc_data_reg[0]),
72 .q_b(del_data_wire),
73 .aclr0(1'b0),
74 .aclr1(1'b0),
75 .addressstall_a(1'b0),
76 .addressstall_b(1'b0),
77 .byteena_a(1'b1),
78 .byteena_b(1'b1),
79 .clock1(1'b1),
80 .clocken0(1'b1),
81 .clocken1(1'b1),
82 .clocken2(1'b1),
83 .clocken3(1'b1),
84 .data_b({(size*widthr){1'b1}}),
85 .eccstatus(),
86 .q_a(),
87 .rden_a(1'b1),
88 .rden_b(1'b1),
89 .wren_b(1'b0));
90
91 lpm_mux #(
92 .lpm_size(2),
93 .lpm_type("LPM_MUX"),
94 .lpm_width(6),
95 .lpm_widths(1)) mux_unit_1 (
96 .sel(int_chan_next),
97 .data({
98 1'b1, int_lfsr_reg[20+4:20],
99 1'b0, int_lfsr_reg[5+4:5]}),
100 .result(int_addr_wire));
101
102 always @(posedge clock)
103 begin
104 if (reset)
105 begin
106 int_wren_reg <= 1'b1;
107 int_flag_reg <= 1'b0;
108 int_chan_reg <= 1'b0;
109 int_case_reg <= 2'd0;
110 int_addr_reg <= 6'd0;
111 for(i = 0; i <= 1; i = i + 1)
112 begin
113 acc_data_reg[i] <= {(size*widthr){1'b0}};
114 end
115 for(i = 0; i <= 2; i = i + 1)
116 begin
117 int_data_reg[i] <= {(size*widthr){1'b0}};
118 end
119 int_lfsr_reg <= 32'd0;
120 end
121 else
122 begin
123 int_wren_reg <= int_wren_next;
124 int_flag_reg <= int_flag_next;
125 int_chan_reg <= int_chan_next;
126 int_case_reg <= int_case_next;
127 int_addr_reg <= int_addr_next;
128 for(i = 0; i <= 1; i = i + 1)
129 begin
130 acc_data_reg[i] <= acc_data_next[i];
131 end
132 for(i = 0; i <= 2; i = i + 1)
133 begin
134 int_data_reg[i] <= int_data_next[i];
135 end
136 int_lfsr_reg <= int_lfsr_next;
137 end
138 end
139
140 always @*
141 begin
142 int_wren_next = int_wren_reg;
143 int_flag_next = int_flag_reg;
144 int_chan_next = int_chan_reg;
145 int_case_next = int_case_reg;
146 int_addr_next = int_addr_reg;
147 for(i = 0; i <= 1; i = i + 1)
148 begin
149 acc_data_next[i] = acc_data_reg[i];
150 end
151 for(i = 0; i <= 2; i = i + 1)
152 begin
153 int_data_next[i] = int_data_reg[i];
154 end
155 int_lfsr_next = int_lfsr_reg;
156
157 case (int_case_reg)
158 0:
159 begin
160 // write zeros
161 int_wren_next = 1'b1;
162 int_addr_next = 6'd0;
163 for(i = 0; i <= 1; i = i + 1)
164 begin
165 acc_data_next[i] = {(size*widthr){1'b0}};
166 end
167 for(i = 0; i <= 2; i = i + 1)
168 begin
169 int_data_next[i] = {(size*widthr){1'b0}};
170 end
171 int_case_next = 2'd1;
172 end
173 1:
174 begin
175 // write zeros
176 int_addr_next = int_addr_reg + 6'd1;
177 if (&int_addr_reg)
178 begin
179 int_wren_next = 1'b0;
180 int_flag_next = 1'b0;
181 int_chan_next = 1'b0;
182 int_lfsr_next = 32'h0722BDA6;
183 int_case_next = 'd2;
184 end
185 end
186 2: // frame
187 begin
188 int_flag_next = 1'b0;
189 if (frame)
190 begin
191 int_wren_next = 1'b1;
192
193 int_addr_next = {1'b0, int_lfsr_reg[4:0]};
194
195 // set read addr for 2nd pipeline
196 int_chan_next = 1'b1;
197
198 // prepare registers for 1st sum
199 acc_data_next[0] = acc_data_wire[0];
200 acc_data_next[1] = int_data_reg[0];
201
202 int_lfsr_next = {int_lfsr_reg[30:0], int_lfsr_reg[2] ~^ int_lfsr_reg[4]};
203
204 int_case_next = 'd3;
205 end
206 if (int_flag_reg) // register 2nd sum
207 begin
208 // register 2nd sum
209 int_data_next[1] = acc_data_wire[1];
210 end
211 end
212 3: // 2nd sum
213 begin
214 int_flag_next = 1'b1;
215
216 int_addr_next = {1'b1, int_lfsr_reg[5:1]};
217
218 // set read addr for 1st pipeline
219 int_chan_next = 1'b0;
220
221 // prepare registers for 2nd sum
222 acc_data_next[0] = int_data_reg[0];
223 acc_data_next[1] = int_data_reg[1];
224
225 // register 1st sum
226 int_data_next[0] = acc_data_wire[1];
227
228 // register 2nd output
229 int_data_next[2] = int_data_reg[1];
230
231 int_case_next = 2'd2;
232 end
233 default:
234 begin
235 int_case_next = 2'd0;
236 end
237 endcase
238 end
239
240 assign out_data = int_data_reg[2];
241
242endmodule
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