[127] | 1 | module filter
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| 2 | #(
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| 3 | parameter size = 3, // number of channels
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| 4 | parameter width = 12 // bit width of the input data (unsigned)
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| 5 | )
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| 6 | (
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| 7 | input wire clock, frame, reset,
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| 8 | input wire [size*width-1:0] inp_data,
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[131] | 9 | output wire [size*widthr-1:0] out_data
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[127] | 10 | );
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| 11 |
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[158] | 12 | localparam widthr = width + 8;
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[127] | 13 | /*
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[156] | 14 | 5-bit LFSR with additional bits to keep track of previous values
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[127] | 15 | */
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[158] | 16 | reg [31:0] int_lfsr_reg, int_lfsr_next;
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[127] | 17 |
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| 18 | reg int_wren_reg, int_wren_next;
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[156] | 19 | reg int_flag_reg, int_flag_next;
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| 20 | reg int_chan_reg, int_chan_next;
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| 21 | reg [1:0] int_case_reg, int_case_next;
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| 22 | reg [5:0] int_addr_reg, int_addr_next;
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[127] | 23 |
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[156] | 24 | wire [5:0] int_addr_wire;
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[127] | 25 |
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[156] | 26 | reg [size*widthr-1:0] acc_data_reg [1:0], acc_data_next [1:0];
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| 27 | reg [size*widthr-1:0] int_data_reg [2:0], int_data_next [2:0];
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[127] | 28 |
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[156] | 29 | wire [size*widthr-1:0] acc_data_wire [1:0], del_data_wire;
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[127] | 30 |
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| 31 | integer i;
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| 32 | genvar j;
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| 33 |
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| 34 | generate
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| 35 | for (j = 0; j < size; j = j + 1)
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| 36 | begin : INT_DATA
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| 37 | assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
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| 38 |
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| 39 | assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
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| 40 | acc_data_reg[0][j*widthr+widthr-1:j*widthr]
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[156] | 41 | - del_data_wire[j*widthr+widthr-1:j*widthr]
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| 42 | + acc_data_reg[1][j*widthr+widthr-1:j*widthr];
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[127] | 43 |
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| 44 | end
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| 45 | endgenerate
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| 46 |
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[156] | 47 | altsyncram #(
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| 48 | .address_aclr_b("NONE"),
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| 49 | .address_reg_b("CLOCK0"),
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| 50 | .clock_enable_input_a("BYPASS"),
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| 51 | .clock_enable_input_b("BYPASS"),
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| 52 | .clock_enable_output_b("BYPASS"),
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| 53 | .intended_device_family("Cyclone III"),
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| 54 | .lpm_type("altsyncram"),
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| 55 | .numwords_a(64),
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| 56 | .numwords_b(64),
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| 57 | .operation_mode("DUAL_PORT"),
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| 58 | .outdata_aclr_b("NONE"),
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| 59 | .outdata_reg_b("CLOCK0"),
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| 60 | .power_up_uninitialized("FALSE"),
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| 61 | .read_during_write_mode_mixed_ports("DONT_CARE"),
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| 62 | .widthad_a(6),
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| 63 | .widthad_b(6),
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| 64 | .width_a(size*widthr),
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| 65 | .width_b(size*widthr),
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| 66 | .width_byteena_a(1)) ram_unit_1 (
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| 67 | .wren_a(int_wren_reg),
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| 68 | .clock0(clock),
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| 69 | .address_a(int_addr_reg),
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| 70 | .address_b(int_addr_wire),
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| 71 | .data_a(acc_data_reg[0]),
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| 72 | .q_b(del_data_wire),
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| 73 | .aclr0(1'b0),
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| 74 | .aclr1(1'b0),
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| 75 | .addressstall_a(1'b0),
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| 76 | .addressstall_b(1'b0),
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| 77 | .byteena_a(1'b1),
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| 78 | .byteena_b(1'b1),
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| 79 | .clock1(1'b1),
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| 80 | .clocken0(1'b1),
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| 81 | .clocken1(1'b1),
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| 82 | .clocken2(1'b1),
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| 83 | .clocken3(1'b1),
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| 84 | .data_b({(size*widthr){1'b1}}),
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| 85 | .eccstatus(),
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| 86 | .q_a(),
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| 87 | .rden_a(1'b1),
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| 88 | .rden_b(1'b1),
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| 89 | .wren_b(1'b0));
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[127] | 90 |
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| 91 | lpm_mux #(
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[156] | 92 | .lpm_size(2),
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[127] | 93 | .lpm_type("LPM_MUX"),
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[156] | 94 | .lpm_width(6),
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| 95 | .lpm_widths(1)) mux_unit_1 (
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[127] | 96 | .sel(int_chan_next),
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| 97 | .data({
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[158] | 98 | 1'b1, int_lfsr_reg[20+4:20],
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| 99 | 1'b0, int_lfsr_reg[5+4:5]}),
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[156] | 100 | .result(int_addr_wire));
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[127] | 101 |
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| 102 | always @(posedge clock)
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| 103 | begin
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| 104 | if (reset)
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| 105 | begin
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| 106 | int_wren_reg <= 1'b1;
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[156] | 107 | int_flag_reg <= 1'b0;
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| 108 | int_chan_reg <= 1'b0;
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| 109 | int_case_reg <= 2'd0;
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| 110 | int_addr_reg <= 6'd0;
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| 111 | for(i = 0; i <= 1; i = i + 1)
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[127] | 112 | begin
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| 113 | acc_data_reg[i] <= {(size*widthr){1'b0}};
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| 114 | end
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[156] | 115 | for(i = 0; i <= 2; i = i + 1)
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[127] | 116 | begin
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| 117 | int_data_reg[i] <= {(size*widthr){1'b0}};
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| 118 | end
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[158] | 119 | int_lfsr_reg <= 32'd0;
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[127] | 120 | end
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| 121 | else
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| 122 | begin
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| 123 | int_wren_reg <= int_wren_next;
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[156] | 124 | int_flag_reg <= int_flag_next;
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[127] | 125 | int_chan_reg <= int_chan_next;
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| 126 | int_case_reg <= int_case_next;
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| 127 | int_addr_reg <= int_addr_next;
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[156] | 128 | for(i = 0; i <= 1; i = i + 1)
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[127] | 129 | begin
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| 130 | acc_data_reg[i] <= acc_data_next[i];
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| 131 | end
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[156] | 132 | for(i = 0; i <= 2; i = i + 1)
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[127] | 133 | begin
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| 134 | int_data_reg[i] <= int_data_next[i];
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| 135 | end
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| 136 | int_lfsr_reg <= int_lfsr_next;
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| 137 | end
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| 138 | end
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| 139 |
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| 140 | always @*
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| 141 | begin
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| 142 | int_wren_next = int_wren_reg;
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[156] | 143 | int_flag_next = int_flag_reg;
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[127] | 144 | int_chan_next = int_chan_reg;
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| 145 | int_case_next = int_case_reg;
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| 146 | int_addr_next = int_addr_reg;
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[156] | 147 | for(i = 0; i <= 1; i = i + 1)
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[127] | 148 | begin
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| 149 | acc_data_next[i] = acc_data_reg[i];
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| 150 | end
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[156] | 151 | for(i = 0; i <= 2; i = i + 1)
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[127] | 152 | begin
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| 153 | int_data_next[i] = int_data_reg[i];
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| 154 | end
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| 155 | int_lfsr_next = int_lfsr_reg;
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| 156 |
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| 157 | case (int_case_reg)
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| 158 | 0:
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| 159 | begin
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| 160 | // write zeros
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| 161 | int_wren_next = 1'b1;
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[156] | 162 | int_addr_next = 6'd0;
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| 163 | for(i = 0; i <= 1; i = i + 1)
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[127] | 164 | begin
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| 165 | acc_data_next[i] = {(size*widthr){1'b0}};
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| 166 | end
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[156] | 167 | for(i = 0; i <= 2; i = i + 1)
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[127] | 168 | begin
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| 169 | int_data_next[i] = {(size*widthr){1'b0}};
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| 170 | end
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[156] | 171 | int_case_next = 2'd1;
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[127] | 172 | end
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| 173 | 1:
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| 174 | begin
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| 175 | // write zeros
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[156] | 176 | int_addr_next = int_addr_reg + 6'd1;
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[127] | 177 | if (&int_addr_reg)
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| 178 | begin
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| 179 | int_wren_next = 1'b0;
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[156] | 180 | int_flag_next = 1'b0;
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| 181 | int_chan_next = 1'b0;
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[158] | 182 | int_lfsr_next = 32'h0722BDA6;
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[156] | 183 | int_case_next = 'd2;
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[127] | 184 | end
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| 185 | end
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| 186 | 2: // frame
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| 187 | begin
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[156] | 188 | int_flag_next = 1'b0;
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[127] | 189 | if (frame)
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| 190 | begin
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| 191 | int_wren_next = 1'b1;
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| 192 |
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[156] | 193 | int_addr_next = {1'b0, int_lfsr_reg[4:0]};
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[127] | 194 |
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| 195 | // set read addr for 2nd pipeline
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[156] | 196 | int_chan_next = 1'b1;
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[127] | 197 |
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| 198 | // prepare registers for 1st sum
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| 199 | acc_data_next[0] = acc_data_wire[0];
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| 200 | acc_data_next[1] = int_data_reg[0];
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| 201 |
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[158] | 202 | int_lfsr_next = {int_lfsr_reg[30:0], int_lfsr_reg[2] ~^ int_lfsr_reg[4]};
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[156] | 203 |
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| 204 | int_case_next = 'd3;
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[127] | 205 | end
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[156] | 206 | if (int_flag_reg) // register 2nd sum
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| 207 | begin
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| 208 | // register 2nd sum
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| 209 | int_data_next[1] = acc_data_wire[1];
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| 210 | end
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[127] | 211 | end
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[156] | 212 | 3: // 2nd sum
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[127] | 213 | begin
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[156] | 214 | int_flag_next = 1'b1;
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[127] | 215 |
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[156] | 216 | int_addr_next = {1'b1, int_lfsr_reg[5:1]};
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[127] | 217 |
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[156] | 218 | // set read addr for 1st pipeline
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| 219 | int_chan_next = 1'b0;
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| 220 |
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[127] | 221 | // prepare registers for 2nd sum
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[156] | 222 | acc_data_next[0] = int_data_reg[0];
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| 223 | acc_data_next[1] = int_data_reg[1];
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[127] | 224 |
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| 225 | // register 1st sum
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| 226 | int_data_next[0] = acc_data_wire[1];
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| 227 |
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[156] | 228 | // register 2nd output
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| 229 | int_data_next[2] = int_data_reg[1];
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[127] | 230 |
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[156] | 231 | int_case_next = 2'd2;
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[127] | 232 | end
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| 233 | default:
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| 234 | begin
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[156] | 235 | int_case_next = 2'd0;
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[127] | 236 | end
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| 237 | endcase
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| 238 | end
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| 239 |
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[156] | 240 | assign out_data = int_data_reg[2];
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[127] | 241 |
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| 242 | endmodule
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