[127] | 1 | module filter
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| 2 | #(
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| 3 | parameter size = 3, // number of channels
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| 4 | parameter width = 12 // bit width of the input data (unsigned)
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| 5 | )
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| 6 | (
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| 7 | input wire clock, frame, reset,
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| 8 | input wire [size*width-1:0] inp_data,
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| 9 | output wire [size*widthr-1:0] out_data,
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| 10 | output wire [size*widthr-1:0] out_data2,
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| 11 | output wire [size*widthr-1:0] out_data3
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| 12 | );
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| 13 |
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| 14 | localparam widthr = width + 13;
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| 15 |
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| 16 | /*
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| 17 | 4-bit LFSR with additional bits to keep track of previous values
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| 18 | */
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| 19 | reg [15:0] int_lfsr_reg, int_lfsr_next;
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| 20 |
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| 21 | reg int_wren_reg, int_wren_next;
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| 22 | reg [1:0] int_chan_reg, int_chan_next;
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| 23 | reg [2:0] int_case_reg, int_case_next;
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| 24 | reg [7:0] int_addr_reg, int_addr_next;
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| 25 |
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| 26 | wire [9:0] int_addr_wire;
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| 27 |
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| 28 | reg [size*widthr-1:0] acc_data_reg [3:0], acc_data_next [3:0];
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| 29 | reg [size*widthr-1:0] int_data_reg [8:0], int_data_next [8:0];
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| 30 |
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| 31 | wire [size*widthr-1:0] acc_data_wire [3:0], del_data_wire [1:0];
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| 32 |
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| 33 | integer i;
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| 34 | genvar j;
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| 35 |
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| 36 | generate
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| 37 | for (j = 0; j < size; j = j + 1)
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| 38 | begin : INT_DATA
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| 39 | assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
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| 40 |
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| 41 | // -2*del_data_1 + del_data_2 + inp_data + result
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| 42 |
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| 43 | assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
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| 44 | acc_data_reg[0][j*widthr+widthr-1:j*widthr]
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| 45 | + del_data_wire[1][j*widthr+widthr-1:j*widthr]
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| 46 | - {del_data_wire[0][j*widthr+widthr-1],del_data_wire[0][j*widthr+widthr-3:j*widthr], 1'b0};
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| 47 |
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| 48 | assign acc_data_wire[2][j*widthr+widthr-1:j*widthr] =
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| 49 | acc_data_reg[1][j*widthr+widthr-1:j*widthr]
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| 50 | + acc_data_reg[2][j*widthr+widthr-1:j*widthr];
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| 51 |
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| 52 | assign acc_data_wire[3][j*widthr+widthr-1:j*widthr] =
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| 53 | acc_data_reg[2][j*widthr+widthr-1:j*widthr]
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| 54 | + acc_data_reg[3][j*widthr+widthr-1:j*widthr];
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| 55 |
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| 56 | end
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| 57 | endgenerate
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| 58 |
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| 59 | cic_pipeline #(
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| 60 | .width(size*widthr)) cic_pipeline_unit (
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| 61 | .clock(clock),
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| 62 | .data(acc_data_reg[0]),
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| 63 | .rdaddress_a({int_addr_wire[9:8], int_addr_wire[3:0]}),
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| 64 | .rdaddress_b({int_addr_wire[9:8], int_addr_wire[7:4]}),
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| 65 | .wraddress(int_addr_reg),
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| 66 | .wren(int_wren_reg),
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| 67 | .qa(del_data_wire[0]),
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| 68 | .qb(del_data_wire[1]));
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| 69 |
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| 70 | lpm_mux #(
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| 71 | .lpm_size(3),
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| 72 | .lpm_type("LPM_MUX"),
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| 73 | .lpm_width(10),
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| 74 | .lpm_widths(2)) mux_unit_1 (
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| 75 | .sel(int_chan_next),
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| 76 | .data({
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| 77 | 2'd2, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5],
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| 78 | 2'd1, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4],
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| 79 | 2'd0, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3]}),
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| 80 | .result(int_addr_wire));
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| 81 |
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| 82 | always @(posedge clock)
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| 83 | begin
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| 84 | if (reset)
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| 85 | begin
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| 86 | int_wren_reg <= 1'b1;
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| 87 | int_chan_reg <= 2'd0;
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| 88 | int_case_reg <= 3'd0;
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| 89 | int_addr_reg <= 8'd0;
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| 90 | for(i = 0; i <= 3; i = i + 1)
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| 91 | begin
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| 92 | acc_data_reg[i] <= {(size*widthr){1'b0}};
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| 93 | end
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| 94 | for(i = 0; i <= 8; i = i + 1)
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| 95 | begin
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| 96 | int_data_reg[i] <= {(size*widthr){1'b0}};
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| 97 | end
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| 98 | int_lfsr_reg <= 16'd0;
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| 99 | end
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| 100 | else
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| 101 | begin
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| 102 | int_wren_reg <= int_wren_next;
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| 103 | int_chan_reg <= int_chan_next;
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| 104 | int_case_reg <= int_case_next;
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| 105 | int_addr_reg <= int_addr_next;
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| 106 | for(i = 0; i <= 3; i = i + 1)
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| 107 | begin
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| 108 | acc_data_reg[i] <= acc_data_next[i];
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| 109 | end
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| 110 | for(i = 0; i <= 8; i = i + 1)
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| 111 | begin
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| 112 | int_data_reg[i] <= int_data_next[i];
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| 113 | end
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| 114 | int_lfsr_reg <= int_lfsr_next;
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| 115 | end
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| 116 | end
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| 117 |
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| 118 | always @*
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| 119 | begin
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| 120 | int_wren_next = int_wren_reg;
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| 121 | int_chan_next = int_chan_reg;
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| 122 | int_case_next = int_case_reg;
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| 123 | int_addr_next = int_addr_reg;
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| 124 | for(i = 0; i <= 3; i = i + 1)
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| 125 | begin
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| 126 | acc_data_next[i] = acc_data_reg[i];
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| 127 | end
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| 128 | for(i = 0; i <= 8; i = i + 1)
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| 129 | begin
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| 130 | int_data_next[i] = int_data_reg[i];
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| 131 | end
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| 132 | int_lfsr_next = int_lfsr_reg;
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| 133 |
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| 134 | case (int_case_reg)
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| 135 | 0:
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| 136 | begin
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| 137 | // write zeros
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| 138 | int_wren_next = 1'b1;
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| 139 | int_addr_next = 8'd0;
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| 140 | for(i = 0; i <= 3; i = i + 1)
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| 141 | begin
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| 142 | acc_data_next[i] = {(size*widthr){1'b0}};
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| 143 | end
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| 144 | for(i = 0; i <= 8; i = i + 1)
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| 145 | begin
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| 146 | int_data_next[i] = {(size*widthr){1'b0}};
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| 147 | end
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| 148 | int_case_next = 3'd1;
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| 149 | end
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| 150 | 1:
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| 151 | begin
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| 152 | // write zeros
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| 153 | int_addr_next = int_addr_reg + 8'd1;
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| 154 | if (&int_addr_reg)
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| 155 | begin
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| 156 | int_wren_next = 1'b0;
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| 157 | int_chan_next = 2'd0;
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| 158 | int_lfsr_next = 16'h7650;
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| 159 | int_case_next = 3'd2;
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| 160 | end
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| 161 | end
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| 162 | 2: // frame
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| 163 | begin
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| 164 | if (frame)
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| 165 | begin
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| 166 | int_wren_next = 1'b1;
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| 167 |
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| 168 | int_addr_next = {4'd0, int_lfsr_reg[3:0]};
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| 169 |
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| 170 | // set read addr for 2nd pipeline
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| 171 | int_chan_next = 2'd1;
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| 172 |
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| 173 | // prepare registers for 1st sum
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| 174 | acc_data_next[0] = acc_data_wire[0];
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| 175 | acc_data_next[1] = int_data_reg[0];
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| 176 | acc_data_next[2] = int_data_reg[1];
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| 177 | acc_data_next[3] = int_data_reg[2];
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| 178 |
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| 179 | int_case_next = 3'd3;
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| 180 | end
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| 181 |
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| 182 | end
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| 183 | 3: // 1st sum
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| 184 | begin
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| 185 | int_addr_next = {4'd1, int_lfsr_reg[3:0]};
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| 186 |
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| 187 | // set read addr for 3rd pipeline
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| 188 | int_chan_next = 2'd2;
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| 189 |
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| 190 | // prepare registers for 2nd sum
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| 191 | acc_data_next[0] = int_data_reg[2];
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| 192 | acc_data_next[1] = int_data_reg[3];
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| 193 | acc_data_next[2] = int_data_reg[4];
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| 194 | acc_data_next[3] = int_data_reg[5];
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| 195 |
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| 196 | // register 1st sum
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| 197 | int_data_next[0] = acc_data_wire[1];
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| 198 | int_data_next[1] = acc_data_wire[2];
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| 199 | int_data_next[2] = acc_data_wire[3];
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| 200 |
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| 201 | int_case_next = 3'd4;
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| 202 | end
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| 203 | 4: // 2nd sum
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| 204 | begin
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| 205 | int_addr_next = {4'd2, int_lfsr_reg[3:0]};
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| 206 |
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| 207 | // prepare registers for 3rd sum
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| 208 | acc_data_next[0] = int_data_reg[5];
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| 209 | acc_data_next[1] = int_data_reg[6];
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| 210 | acc_data_next[2] = int_data_reg[7];
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| 211 | acc_data_next[3] = int_data_reg[8];
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| 212 |
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| 213 | // register 2nd sum
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| 214 | int_data_next[3] = acc_data_wire[1];
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| 215 | int_data_next[4] = acc_data_wire[2];
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| 216 | int_data_next[5] = acc_data_wire[3];
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| 217 |
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| 218 | int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]};
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| 219 |
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| 220 | int_case_next = 3'd5;
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| 221 | end
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| 222 | 5: // 3rd sum
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| 223 | begin
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| 224 | int_wren_next = 1'b0;
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| 225 |
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| 226 | // set read addr for 1st pipeline
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| 227 | int_chan_next = 2'd0;
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| 228 |
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| 229 | // register 3rd sum
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| 230 | int_data_next[6] = acc_data_wire[1];
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| 231 | int_data_next[7] = acc_data_wire[2];
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| 232 | int_data_next[8] = acc_data_wire[3];
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| 233 |
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| 234 | int_case_next = 3'd2;
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| 235 | end
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| 236 | default:
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| 237 | begin
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| 238 | int_case_next = 3'd0;
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| 239 | end
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| 240 | endcase
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| 241 | end
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| 242 |
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| 243 | assign out_data = int_data_reg[2];
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| 244 | assign out_data2 = int_data_reg[5];
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| 245 | assign out_data3 = int_data_reg[8];
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| 246 |
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| 247 | endmodule
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