Last change
on this file since 185 was 107, checked in by demin, 14 years ago |
Starting to test signal shaping algorithms
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File size:
653 bytes
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Rev | Line | |
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[107] | 1 | module delay
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| 2 | #(
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| 3 | parameter width = 12,
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| 4 | parameter length = 32
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| 5 | )
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| 6 | (
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| 7 | input wire clock, frame, reset,
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| 8 | input wire [width-1:0] inp_data,
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| 9 | output wire [width-1:0] out_data
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| 10 | );
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| 11 |
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| 12 | reg [width-1:0] int_pipe_reg [length-1:0];
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| 13 |
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| 14 | integer i;
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| 15 |
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| 16 | always @(posedge clock)
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| 17 | begin
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| 18 | if (reset)
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| 19 | begin
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| 20 | for(i = 0; i < length; i = i + 1)
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| 21 | begin
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| 22 | int_pipe_reg[i] <= 0;
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| 23 | end
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| 24 | end
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| 25 | else if (frame)
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| 26 | begin
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| 27 | for(i = 0; i <= 30; i = i + 1)
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| 28 | begin
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| 29 | int_pipe_reg[i+1] <= int_pipe_reg[i];
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| 30 | end
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| 31 | int_pipe_reg[0] <= inp_data;
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| 32 | end
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| 33 | end
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| 34 |
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| 35 | assign out_data = int_pipe_reg[length-1];
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| 36 |
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| 37 | endmodule
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