source: sandbox/MultiChannelUSB/deconv.v@ 121

Last change on this file since 121 was 120, checked in by demin, 14 years ago

add shifter
File size: 11.3 KB
Line 
1module deconv
2 #(
3 parameter size = 1, // number of channels
4 parameter width = 24 // bit width of the input data
5 )
6 (
7 input wire clock, frame, reset,
8 input wire [3*size*6-1:0] del_data,
9 input wire [3*size*8-1:0] amp_data,
10 input wire [3*size*16-1:0] tau_data,
11 input wire [3*size*6-1:0] cls_data,
12 input wire [3*size*width-1:0] inp_data,
13 output wire [3*size*widthr-1:0] out_data
14 );
15
16 localparam width1 = width + 1;
17 localparam width2 = width + 6 + 1;
18 localparam widthr = width + 16 + 3;
19
20 reg int_wren_reg, int_wren_next;
21 reg [1:0] int_chan_reg, int_chan_next;
22 reg [2:0] int_case_reg, int_case_next;
23 reg [7:0] int_addr_reg, int_addr_next;
24
25 reg [5:0] del_addr_reg, del_addr_next;
26 wire [5:0] del_addr_wire;
27 wire [7:0] int_addr_wire;
28
29 reg [size*widthr-1:0] out_data_reg [2:0], out_data_next [2:0];
30 wire [size*widthr-1:0] out_data_wire;
31
32 wire [size*widthr-1:0] add_data_wire;
33
34 wire [size*widthr-1:0] mul_data_wire [1:0];
35
36 reg [size*width2-1:0] acc_data_reg [3:0], acc_data_next [3:0];
37 wire [size*width2-1:0] acc_data_wire;
38
39 wire [size*width1-1:0] sub_data_wire;
40
41 reg [size*width-1:0] inp_data_reg [2:0], inp_data_next [2:0];
42 wire [size*width-1:0] inp_data_wire [3:0];
43
44 reg [size*8-1:0] amp_data_reg, amp_data_next;
45 wire [size*8-1:0] amp_data_wire [2:0];
46
47 reg [size*16-1:0] tau_data_reg, tau_data_next;
48 wire [size*16-1:0] tau_data_wire [2:0];
49
50 reg [size*6-1:0] cls_data_reg, cls_data_next;
51 wire [size*6-1:0] cls_data_wire [2:0];
52
53 integer i;
54 genvar j;
55
56 generate
57 for (j = 0; j < size; j = j + 1)
58 begin : INT_DATA
59 assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(3*j+0)*width+width-1:(3*j+0)*width];
60 assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(3*j+1)*width+width-1:(3*j+1)*width];
61 assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(3*j+2)*width+width-1:(3*j+2)*width];
62 assign amp_data_wire[0][j*8+8-1:j*8] = amp_data[(3*j+0)*8+8-1:(3*j+0)*8];
63 assign amp_data_wire[1][j*8+8-1:j*8] = amp_data[(3*j+1)*8+8-1:(3*j+1)*8];
64 assign amp_data_wire[2][j*8+8-1:j*8] = amp_data[(3*j+2)*8+8-1:(3*j+2)*8];
65 assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(3*j+0)*16+16-1:(3*j+0)*16];
66 assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(3*j+1)*16+16-1:(3*j+1)*16];
67 assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(3*j+2)*16+16-1:(3*j+2)*16];
68 assign cls_data_wire[0][j*6+6-1:j*6] = cls_data[(3*j+0)*6+6-1:(3*j+0)*6];
69 assign cls_data_wire[1][j*6+6-1:j*6] = cls_data[(3*j+1)*6+6-1:(3*j+1)*6];
70 assign cls_data_wire[2][j*6+6-1:j*6] = cls_data[(3*j+2)*6+6-1:(3*j+2)*6];
71
72 lpm_mux #(
73 .lpm_size(3),
74 .lpm_type("LPM_MUX"),
75 .lpm_width(8),
76 .lpm_widths(2)) mux_unit_1 (
77 .sel(int_chan_next),
78 .data({
79 2'd2, del_data[(3*j+2)*6+6-1:(3*j+2)*6],
80 2'd1, del_data[(3*j+1)*6+6-1:(3*j+1)*6],
81 2'd0, del_data[(3*j+0)*6+6-1:(3*j+0)*6]}),
82 .result(int_addr_wire));
83
84 lpm_add_sub #(
85 .lpm_direction("SUB"),
86 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
87 .lpm_representation("UNSIGNED"),
88 .lpm_type("LPM_ADD_SUB"),
89 .lpm_width(6)) add_unit_1 (
90 .dataa(del_addr_reg),
91 .datab(int_addr_wire[5:0]),
92 .result(del_addr_wire));
93
94 lpm_add_sub #(
95 .lpm_direction("SUB"),
96 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
97 .lpm_representation("SIGNED"),
98 .lpm_type("LPM_ADD_SUB"),
99 .lpm_width(width1)) sub_unit_1 (
100 .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}),
101 .datab({{(width1-width){1'b0}}, inp_data_wire[3][j*width+width-1:j*width]}),
102 .result(sub_data_wire[j*width1+width1-1:j*width1]));
103
104 lpm_add_sub #(
105 .lpm_direction("ADD"),
106 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
107 .lpm_representation("SIGNED"),
108 .lpm_type("LPM_ADD_SUB"),
109 .lpm_width(width2)) acc_unit_1 (
110 .dataa({{(width2-width1+1){sub_data_wire[j*width1+width1-1]}}, sub_data_wire[j*width1+width1-2:j*width1]}),
111 .datab(acc_data_reg[0][j*width2+width2-1:j*width2]),
112 .result(acc_data_wire[j*width2+width2-1:j*width2]));
113
114 lpm_mult #(
115 .lpm_hint("MAXIMIZE_SPEED=9"),
116 .lpm_representation("SIGNED"),
117 .lpm_type("LPM_MULT"),
118 .lpm_pipeline(3),
119 .lpm_widtha(width1),
120 .lpm_widthb(17),
121 .lpm_widthp(widthr)) mult_unit_1 (
122 .clock(clock),
123 .clken(int_wren_reg),
124 .dataa(sub_data_wire[j*width1+width1-1:j*width1]),
125 .datab({1'b0, tau_data_reg[j*16+16-1:j*16]}),
126 .result(mul_data_wire[0][j*widthr+widthr-1:j*widthr]));
127
128 lpm_mult #(
129 .lpm_hint("MAXIMIZE_SPEED=9"),
130 .lpm_representation("UNSIGNED"),
131 .lpm_type("LPM_MULT"),
132 .lpm_pipeline(3),
133 .lpm_widtha(width2),
134 .lpm_widthb(8),
135 .lpm_widthp(widthr)) mult_unit_2 (
136 .clock(clock),
137 .clken(int_wren_reg),
138 .dataa(acc_data_reg[0][j*width2+width2-1:j*width2]),
139 .datab(amp_data_reg[j*8+8-1:j*8]),
140 .result(mul_data_wire[1][j*widthr+widthr-1:j*widthr]));
141
142 lpm_add_sub #(
143 .lpm_direction("ADD"),
144 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
145 .lpm_representation("SIGNED"),
146 .lpm_type("LPM_ADD_SUB"),
147 .lpm_width(widthr)) add_unit_2 (
148 .dataa(mul_data_wire[0][j*widthr+widthr-1:j*widthr]),
149 .datab(mul_data_wire[1][j*widthr+widthr-1:j*widthr]),
150 .result(add_data_wire[j*widthr+widthr-1:j*widthr]));
151
152
153 lpm_clshift #(
154 .lpm_shifttype("LOGICAL"),
155 .lpm_type("LPM_CLSHIFT"),
156 .lpm_width(widthr),
157 .lpm_widthdist(6)) shift_unit_1 (
158 .distance(cls_data_reg[j*6+6-1:j*6]),
159 .direction(1'b1),
160 .data(add_data_wire[j*widthr+widthr-1:j*widthr]),
161 .result(out_data_wire[j*widthr+widthr-1:j*widthr]));
162
163 end
164 endgenerate
165
166
167 altsyncram #(
168 .address_aclr_b("NONE"),
169 .address_reg_b("CLOCK0"),
170 .clock_enable_input_a("BYPASS"),
171 .clock_enable_input_b("BYPASS"),
172 .clock_enable_output_b("BYPASS"),
173 .intended_device_family("Cyclone III"),
174 .lpm_type("altsyncram"),
175 .numwords_a(256),
176 .numwords_b(256),
177 .operation_mode("DUAL_PORT"),
178 .outdata_aclr_b("NONE"),
179 .outdata_reg_b("CLOCK0"),
180 .power_up_uninitialized("FALSE"),
181 .read_during_write_mode_mixed_ports("DONT_CARE"),
182 .widthad_a(8),
183 .widthad_b(8),
184 .width_a(size*width),
185 .width_b(size*width),
186 .width_byteena_a(1)) ram_unit_1 (
187 .wren_a(int_wren_reg),
188 .clock0(clock),
189 .address_a(int_addr_reg),
190 .address_b({int_addr_wire[7:6], del_addr_wire}),
191 .data_a(inp_data_reg[0]),
192 .q_b(inp_data_wire[3]),
193 .aclr0(1'b0),
194 .aclr1(1'b0),
195 .addressstall_a(1'b0),
196 .addressstall_b(1'b0),
197 .byteena_a(1'b1),
198 .byteena_b(1'b1),
199 .clock1(1'b1),
200 .clocken0(1'b1),
201 .clocken1(1'b1),
202 .clocken2(1'b1),
203 .clocken3(1'b1),
204 .data_b({(size*width){1'b1}}),
205 .eccstatus(),
206 .q_a(),
207 .rden_a(1'b1),
208 .rden_b(1'b1),
209 .wren_b(1'b0));
210
211 always @(posedge clock)
212 begin
213 if (reset)
214 begin
215 int_wren_reg <= 1'b1;
216 int_chan_reg <= 2'd0;
217 int_case_reg <= 3'd0;
218 del_addr_reg <= 6'd0;
219 int_addr_reg <= 8'd0;
220 amp_data_reg <= 8'd0;
221 tau_data_reg <= 16'd0;
222 cls_data_reg <= 6'd0;
223 for(i = 0; i <= 2; i = i + 1)
224 begin
225 inp_data_reg[i] <= {(size*width){1'b0}};
226 out_data_reg[i] <= {(size*widthr){1'b0}};
227 end
228 for(i = 0; i <= 3; i = i + 1)
229 begin
230 acc_data_reg[i] <= {(size*width2){1'b0}};
231 end
232 end
233 else
234 begin
235 int_wren_reg <= int_wren_next;
236 int_chan_reg <= int_chan_next;
237 int_case_reg <= int_case_next;
238 del_addr_reg <= del_addr_next;
239 int_addr_reg <= int_addr_next;
240 amp_data_reg <= amp_data_next;
241 tau_data_reg <= tau_data_next;
242 cls_data_reg <= cls_data_next;
243 for(i = 0; i <= 2; i = i + 1)
244 begin
245 inp_data_reg[i] <= inp_data_next[i];
246 out_data_reg[i] <= out_data_next[i];
247 end
248 for(i = 0; i <= 3; i = i + 1)
249 begin
250 acc_data_reg[i] <= acc_data_next[i];
251 end
252 end
253 end
254
255 always @*
256 begin
257 int_wren_next = int_wren_reg;
258 int_chan_next = int_chan_reg;
259 int_case_next = int_case_reg;
260 del_addr_next = del_addr_reg;
261 int_addr_next = int_addr_reg;
262 amp_data_next = amp_data_reg;
263 tau_data_next = tau_data_reg;
264 cls_data_next = cls_data_reg;
265 for(i = 0; i <= 2; i = i + 1)
266 begin
267 inp_data_next[i] = inp_data_reg[i];
268 out_data_next[i] = out_data_reg[i];
269 end
270 for(i = 0; i <= 3; i = i + 1)
271 begin
272 acc_data_next[i] = acc_data_reg[i];
273 end
274
275 case (int_case_reg)
276 0:
277 begin
278 // write zeros
279 int_wren_next = 1'b1;
280 del_addr_next = 6'd0;
281 int_addr_next = 8'd0;
282 amp_data_next = 8'd0;
283 tau_data_next = 16'd0;
284 cls_data_next = 6'd0;
285 for(i = 0; i <= 2; i = i + 1)
286 begin
287 inp_data_next[i] = {(size*width){1'b0}};
288 out_data_next[i] = {(size*widthr){1'b0}};
289 end
290 for(i = 0; i <= 3; i = i + 1)
291 begin
292 acc_data_next[i] = {(size*width2){1'b0}};
293 end
294
295 int_case_next = 3'd1;
296 end
297 1:
298 begin
299 // write zeros
300 int_addr_next = int_addr_reg + 8'd1;
301 if (&int_addr_reg)
302 begin
303 int_wren_next = 1'b0;
304 int_chan_next = 2'd0;
305 int_case_next = 3'd2;
306 end
307 end
308 2: // frame
309 begin
310 if (frame)
311 begin
312 int_wren_next = 1'b1;
313
314 int_addr_next[7:6] = 2'd0;
315
316 // set read addr for 2nd pipeline
317 int_chan_next = 2'd1;
318
319 // register input data for 2nd and 3rd sums
320 inp_data_next[1] = inp_data_wire[1];
321 inp_data_next[2] = inp_data_wire[2];
322
323 // prepare registers for 1st sum
324 inp_data_next[0] = inp_data_wire[0];
325 acc_data_next[0] = acc_data_reg[1];
326
327 tau_data_next = tau_data_wire[0];
328 amp_data_next = amp_data_wire[0];
329 cls_data_next = cls_data_wire[0];
330
331 int_case_next = 3'd3;
332 end
333
334 end
335 3: // 1st sum
336 begin
337 int_addr_next[7:6] = 2'd1;
338
339 // set read addr for 3rd pipeline
340 int_chan_next = 2'd2;
341
342 // prepare registers for 2nd sum
343 inp_data_next[0] = inp_data_reg[1];
344 acc_data_next[0] = acc_data_reg[2];
345
346 tau_data_next = tau_data_wire[1];
347 amp_data_next = amp_data_wire[1];
348 cls_data_next = cls_data_wire[1];
349
350 // register 1st sum
351 acc_data_next[1] = acc_data_wire;
352 out_data_next[0] = out_data_wire;
353
354 int_case_next = 3'd4;
355 end
356 4: // 2nd sum
357 begin
358 int_addr_next[7:6] = 2'd2;
359
360 // prepare registers for 3rd sum
361 inp_data_next[0] = inp_data_reg[2];
362 acc_data_next[0] = acc_data_reg[3];
363
364 tau_data_next = tau_data_wire[2];
365 amp_data_next = amp_data_wire[2];
366 cls_data_next = cls_data_wire[2];
367
368 // register 2nd sum
369 acc_data_next[2] = acc_data_wire;
370 out_data_next[1] = out_data_wire;
371
372 del_addr_next = del_addr_reg + 6'd1;
373
374 int_case_next = 3'd5;
375 end
376 5: // 3rd sum
377 begin
378 int_wren_next = 1'b0;
379
380 // set read addr for 1st pipeline
381 int_chan_next = 2'd0;
382
383 // register 3rd sum
384 acc_data_next[3] = acc_data_wire;
385 out_data_next[2] = out_data_wire;
386
387 int_addr_next[5:0] = del_addr_reg;
388
389 int_case_next = 3'd2;
390 end
391 default:
392 begin
393 int_case_next = 3'd0;
394 end
395 endcase
396 end
397
398 assign out_data = {out_data_reg[2], out_data_reg[1], out_data_reg[0]};
399
400endmodule
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