source: sandbox/MultiChannelUSB/deconv.v@ 118

Last change on this file since 118 was 118, checked in by demin, 14 years ago

replace removed register with wire
File size: 10.6 KB
RevLine 
[113]1module deconv
2 #(
3 parameter size = 1, // number of channels
[117]4 parameter width = 24 // bit width of the input data
[113]5 )
6 (
7 input wire clock, frame, reset,
[114]8 input wire [3*size*6-1:0] del_data,
9 input wire [3*size*8-1:0] amp_data,
10 input wire [3*size*16-1:0] tau_data,
[113]11 input wire [3*size*width-1:0] inp_data,
[116]12 output wire [3*size*widthr-1:0] out_data
[113]13 );
14
[114]15 localparam width1 = width + 1;
16 localparam width2 = width + 6 + 1;
17 localparam widthr = width + 16 + 3;
[113]18
19 reg int_wren_reg, int_wren_next;
20 reg [1:0] int_chan_reg, int_chan_next;
21 reg [2:0] int_case_reg, int_case_next;
22 reg [7:0] int_addr_reg, int_addr_next;
23
[114]24 reg [5:0] del_addr_reg, del_addr_next;
25 wire [5:0] del_addr_wire;
[113]26 wire [7:0] int_addr_wire;
27
[114]28 reg [size*widthr-1:0] out_data_reg [2:0], out_data_next [2:0];
29 wire [size*widthr-1:0] out_data_wire;
[113]30
[114]31 wire [size*widthr-1:0] mul_data_wire [1:0];
[113]32
[114]33 reg [size*width2-1:0] acc_data_reg [3:0], acc_data_next [3:0];
34 wire [size*width2-1:0] acc_data_wire;
[113]35
[114]36 wire [size*width1-1:0] sub_data_wire;
37
38 reg [size*width-1:0] inp_data_reg [2:0], inp_data_next [2:0];
39 wire [size*width-1:0] inp_data_wire [3:0];
40
41 reg [size*8-1:0] amp_data_reg, amp_data_next;
42 wire [size*8-1:0] amp_data_wire [2:0];
43
44 reg [size*16-1:0] tau_data_reg, tau_data_next;
45 wire [size*16-1:0] tau_data_wire [2:0];
46
[113]47 integer i;
48 genvar j;
49
50 generate
51 for (j = 0; j < size; j = j + 1)
52 begin : INT_DATA
[114]53 assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(3*j+0)*width+width-1:(3*j+0)*width];
54 assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(3*j+1)*width+width-1:(3*j+1)*width];
55 assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(3*j+2)*width+width-1:(3*j+2)*width];
56 assign amp_data_wire[0][j*8+8-1:j*8] = amp_data[(3*j+0)*8+8-1:(3*j+0)*8];
57 assign amp_data_wire[1][j*8+8-1:j*8] = amp_data[(3*j+1)*8+8-1:(3*j+1)*8];
58 assign amp_data_wire[2][j*8+8-1:j*8] = amp_data[(3*j+2)*8+8-1:(3*j+2)*8];
59 assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(3*j+0)*16+16-1:(3*j+0)*16];
60 assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(3*j+1)*16+16-1:(3*j+1)*16];
61 assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(3*j+2)*16+16-1:(3*j+2)*16];
[113]62
[114]63 lpm_mux #(
64 .lpm_size(3),
65 .lpm_type("LPM_MUX"),
66 .lpm_width(8),
67 .lpm_widths(2)) mux_unit_1 (
68 .sel(int_chan_next),
69 .data({
70 2'd2, del_data[(3*j+2)*6+6-1:(3*j+2)*6],
71 2'd1, del_data[(3*j+1)*6+6-1:(3*j+1)*6],
72 2'd0, del_data[(3*j+0)*6+6-1:(3*j+0)*6]}),
73 .result(int_addr_wire));
74
[113]75 lpm_add_sub #(
[114]76 .lpm_direction("SUB"),
[113]77 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
78 .lpm_representation("UNSIGNED"),
79 .lpm_type("LPM_ADD_SUB"),
80 .lpm_width(6)) add_unit_1 (
[114]81 .dataa(del_addr_reg),
[113]82 .datab(int_addr_wire[5:0]),
83 .result(del_addr_wire));
84
85 lpm_add_sub #(
86 .lpm_direction("SUB"),
87 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
88 .lpm_representation("SIGNED"),
89 .lpm_type("LPM_ADD_SUB"),
[114]90 .lpm_width(width1)) sub_unit_1 (
91 .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}),
92 .datab({{(width1-width){1'b0}}, inp_data_wire[3][j*width+width-1:j*width]}),
93 .result(sub_data_wire[j*width1+width1-1:j*width1]));
[113]94
95 lpm_add_sub #(
96 .lpm_direction("ADD"),
97 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
98 .lpm_representation("SIGNED"),
99 .lpm_type("LPM_ADD_SUB"),
[114]100 .lpm_width(width2)) acc_unit_1 (
[118]101 .dataa({{(width2-width1+1){sub_data_wire[j*width1+width1-1]}}, sub_data_wire[j*width1+width1-2:j*width1]}),
[114]102 .datab(acc_data_reg[0][j*width2+width2-1:j*width2]),
103 .result(acc_data_wire[j*width2+width2-1:j*width2]));
[113]104
105 lpm_mult #(
106 .lpm_hint("MAXIMIZE_SPEED=9"),
107 .lpm_representation("SIGNED"),
108 .lpm_type("LPM_MULT"),
109 .lpm_pipeline(3),
[114]110 .lpm_widtha(width1),
111 .lpm_widthb(17),
112 .lpm_widthp(widthr)) mult_unit_1 (
[113]113 .clock(clock),
114 .clken(int_wren_reg),
[117]115 .dataa(sub_data_wire[j*width1+width1-1:j*width1]),
[114]116 .datab({1'b0, tau_data_reg[j*16+16-1:j*16]}),
117 .result(mul_data_wire[0][j*widthr+widthr-1:j*widthr]));
[113]118
119 lpm_mult #(
120 .lpm_hint("MAXIMIZE_SPEED=9"),
[114]121 .lpm_representation("UNSIGNED"),
[113]122 .lpm_type("LPM_MULT"),
123 .lpm_pipeline(3),
[114]124 .lpm_widtha(width2),
125 .lpm_widthb(8),
[113]126 .lpm_widthp(widthr)) mult_unit_2 (
127 .clock(clock),
128 .clken(int_wren_reg),
[114]129 .dataa(acc_data_reg[0][j*width2+width2-1:j*width2]),
130 .datab(amp_data_reg[j*8+8-1:j*8]),
131 .result(mul_data_wire[1][j*widthr+widthr-1:j*widthr]));
[113]132
133 lpm_add_sub #(
134 .lpm_direction("ADD"),
135 .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
136 .lpm_representation("SIGNED"),
137 .lpm_type("LPM_ADD_SUB"),
138 .lpm_width(widthr)) add_unit_2 (
[117]139 .dataa(mul_data_wire[0][j*widthr+widthr-1:j*widthr]),
140 .datab(mul_data_wire[1][j*widthr+widthr-1:j*widthr]),
[114]141 .result(out_data_wire[j*widthr+widthr-1:j*widthr]));
[113]142
[117]143/*
144 lpm_clshift #(
145 .lpm_shifttype("LOGICAL"),
146 .lpm_type("LPM_CLSHIFT"),
147 .lpm_width(64),
148 .lpm_widthdist(6)) shift_unit_1 (
149 .distance(distance),
150 .direction(sub_wire1),
151 .data(data),
152 .result(sub_wire0));
153*/
[113]154 end
155 endgenerate
156
157
158 altsyncram #(
159 .address_aclr_b("NONE"),
160 .address_reg_b("CLOCK0"),
161 .clock_enable_input_a("BYPASS"),
162 .clock_enable_input_b("BYPASS"),
163 .clock_enable_output_b("BYPASS"),
164 .intended_device_family("Cyclone III"),
165 .lpm_type("altsyncram"),
166 .numwords_a(256),
167 .numwords_b(256),
168 .operation_mode("DUAL_PORT"),
169 .outdata_aclr_b("NONE"),
170 .outdata_reg_b("CLOCK0"),
171 .power_up_uninitialized("FALSE"),
172 .read_during_write_mode_mixed_ports("DONT_CARE"),
173 .widthad_a(8),
174 .widthad_b(8),
[114]175 .width_a(size*width),
176 .width_b(size*width),
[113]177 .width_byteena_a(1)) ram_unit_1 (
178 .wren_a(int_wren_reg),
179 .clock0(clock),
180 .address_a(int_addr_reg),
181 .address_b({int_addr_wire[7:6], del_addr_wire}),
[114]182 .data_a(inp_data_reg[0]),
183 .q_b(inp_data_wire[3]),
[113]184 .aclr0(1'b0),
185 .aclr1(1'b0),
186 .addressstall_a(1'b0),
187 .addressstall_b(1'b0),
188 .byteena_a(1'b1),
189 .byteena_b(1'b1),
190 .clock1(1'b1),
191 .clocken0(1'b1),
192 .clocken1(1'b1),
193 .clocken2(1'b1),
194 .clocken3(1'b1),
[114]195 .data_b({(size*width){1'b1}}),
[113]196 .eccstatus(),
197 .q_a(),
198 .rden_a(1'b1),
199 .rden_b(1'b1),
200 .wren_b(1'b0));
201
202 always @(posedge clock)
203 begin
204 if (reset)
205 begin
206 int_wren_reg <= 1'b1;
207 int_chan_reg <= 2'd0;
208 int_case_reg <= 3'd0;
[114]209 del_addr_reg <= 6'd0;
[113]210 int_addr_reg <= 8'd0;
[114]211 amp_data_reg <= 8'd0;
212 tau_data_reg <= 16'd0;
213 for(i = 0; i <= 2; i = i + 1)
[113]214 begin
[114]215 inp_data_reg[i] <= {(size*width){1'b0}};
216 out_data_reg[i] <= {(size*widthr){1'b0}};
[113]217 end
[114]218 for(i = 0; i <= 3; i = i + 1)
[113]219 begin
[114]220 acc_data_reg[i] <= {(size*width2){1'b0}};
[113]221 end
222 end
223 else
224 begin
225 int_wren_reg <= int_wren_next;
226 int_chan_reg <= int_chan_next;
227 int_case_reg <= int_case_next;
[114]228 del_addr_reg <= del_addr_next;
[113]229 int_addr_reg <= int_addr_next;
[114]230 amp_data_reg <= amp_data_next;
231 tau_data_reg <= tau_data_next;
232 for(i = 0; i <= 2; i = i + 1)
[113]233 begin
[114]234 inp_data_reg[i] <= inp_data_next[i];
235 out_data_reg[i] <= out_data_next[i];
236 end
237 for(i = 0; i <= 3; i = i + 1)
238 begin
[113]239 acc_data_reg[i] <= acc_data_next[i];
[114]240 end
[113]241 end
242 end
243
244 always @*
245 begin
246 int_wren_next = int_wren_reg;
247 int_chan_next = int_chan_reg;
248 int_case_next = int_case_reg;
[114]249 del_addr_next = del_addr_reg;
[113]250 int_addr_next = int_addr_reg;
[114]251 amp_data_next = amp_data_reg;
252 tau_data_next = tau_data_reg;
253 for(i = 0; i <= 2; i = i + 1)
[113]254 begin
[114]255 inp_data_next[i] = inp_data_reg[i];
256 out_data_next[i] = out_data_reg[i];
257 end
258 for(i = 0; i <= 3; i = i + 1)
259 begin
[113]260 acc_data_next[i] = acc_data_reg[i];
[114]261 end
[113]262
263 case (int_case_reg)
264 0:
265 begin
266 // write zeros
267 int_wren_next = 1'b1;
[114]268 del_addr_next = 6'd0;
[113]269 int_addr_next = 8'd0;
[114]270 amp_data_next = 8'd0;
271 tau_data_next = 16'd0;
272 for(i = 0; i <= 2; i = i + 1)
[113]273 begin
[114]274 inp_data_next[i] = {(size*width){1'b0}};
275 out_data_next[i] = {(size*widthr){1'b0}};
276 end
277 for(i = 0; i <= 3; i = i + 1)
[113]278 begin
[114]279 acc_data_next[i] = {(size*width2){1'b0}};
280 end
281
[113]282 int_case_next = 3'd1;
283 end
284 1:
285 begin
286 // write zeros
287 int_addr_next = int_addr_reg + 8'd1;
288 if (&int_addr_reg)
289 begin
290 int_wren_next = 1'b0;
291 int_chan_next = 2'd0;
292 int_case_next = 3'd2;
293 end
294 end
295 2: // frame
296 begin
297 if (frame)
298 begin
299 int_wren_next = 1'b1;
300
301 int_addr_next[7:6] = 2'd0;
302
303 // set read addr for 2nd pipeline
304 int_chan_next = 2'd1;
305
306 // register input data for 2nd and 3rd sums
[114]307 inp_data_next[1] = inp_data_wire[1];
308 inp_data_next[2] = inp_data_wire[2];
[113]309
310 // prepare registers for 1st sum
[114]311 inp_data_next[0] = inp_data_wire[0];
312 acc_data_next[0] = acc_data_reg[1];
313
314 tau_data_next = tau_data_wire[0];
315 amp_data_next = amp_data_wire[0];
316
[113]317 int_case_next = 3'd3;
318 end
319
320 end
321 3: // 1st sum
322 begin
323 int_addr_next[7:6] = 2'd1;
324
325 // set read addr for 3rd pipeline
326 int_chan_next = 2'd2;
327
328 // prepare registers for 2nd sum
[114]329 inp_data_next[0] = inp_data_reg[1];
330 acc_data_next[0] = acc_data_reg[2];
331
332 tau_data_next = tau_data_wire[1];
333 amp_data_next = amp_data_wire[1];
334
[113]335 // register 1st sum
[114]336 acc_data_next[1] = acc_data_wire;
337 out_data_next[0] = out_data_wire;
[113]338
339 int_case_next = 3'd4;
340 end
341 4: // 2nd sum
342 begin
343 int_addr_next[7:6] = 2'd2;
344
345 // prepare registers for 3rd sum
[114]346 inp_data_next[0] = inp_data_reg[2];
347 acc_data_next[0] = acc_data_reg[3];
348
349 tau_data_next = tau_data_wire[2];
350 amp_data_next = amp_data_wire[2];
[113]351
352 // register 2nd sum
[114]353 acc_data_next[2] = acc_data_wire;
354 out_data_next[1] = out_data_wire;
[113]355
[114]356 del_addr_next = del_addr_reg + 6'd1;
357
[113]358 int_case_next = 3'd5;
359 end
360 5: // 3rd sum
361 begin
362 int_wren_next = 1'b0;
363
364 // set read addr for 1st pipeline
365 int_chan_next = 2'd0;
366
367 // register 3rd sum
[114]368 acc_data_next[3] = acc_data_wire;
369 out_data_next[2] = out_data_wire;
[113]370
[114]371 int_addr_next[5:0] = del_addr_reg;
[113]372
373 int_case_next = 3'd2;
374 end
375 default:
376 begin
377 int_case_next = 3'd0;
378 end
379 endcase
380 end
381
[114]382 assign out_data = {out_data_reg[2], out_data_reg[1], out_data_reg[0]};
[113]383
384endmodule
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