[113] | 1 | module deconv
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| 2 | #(
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| 3 | parameter size = 1, // number of channels
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[117] | 4 | parameter width = 24 // bit width of the input data
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[113] | 5 | )
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| 6 | (
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| 7 | input wire clock, frame, reset,
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[114] | 8 | input wire [3*size*6-1:0] del_data,
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| 9 | input wire [3*size*8-1:0] amp_data,
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| 10 | input wire [3*size*16-1:0] tau_data,
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[113] | 11 | input wire [3*size*width-1:0] inp_data,
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[116] | 12 | output wire [3*size*widthr-1:0] out_data
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[113] | 13 | );
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| 14 |
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[114] | 15 | localparam width1 = width + 1;
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| 16 | localparam width2 = width + 6 + 1;
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| 17 | localparam widthr = width + 16 + 3;
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[113] | 18 |
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| 19 | reg int_wren_reg, int_wren_next;
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| 20 | reg [1:0] int_chan_reg, int_chan_next;
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| 21 | reg [2:0] int_case_reg, int_case_next;
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| 22 | reg [7:0] int_addr_reg, int_addr_next;
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| 23 |
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[114] | 24 | reg [5:0] del_addr_reg, del_addr_next;
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| 25 | wire [5:0] del_addr_wire;
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[113] | 26 | wire [7:0] int_addr_wire;
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| 27 |
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[114] | 28 | reg [size*widthr-1:0] out_data_reg [2:0], out_data_next [2:0];
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| 29 | wire [size*widthr-1:0] out_data_wire;
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[113] | 30 |
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[114] | 31 | wire [size*widthr-1:0] mul_data_wire [1:0];
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[113] | 32 |
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[114] | 33 | reg [size*width2-1:0] acc_data_reg [3:0], acc_data_next [3:0];
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| 34 | wire [size*width2-1:0] acc_data_wire;
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[113] | 35 |
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[114] | 36 | wire [size*width1-1:0] sub_data_wire;
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| 37 |
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| 38 | reg [size*width-1:0] inp_data_reg [2:0], inp_data_next [2:0];
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| 39 | wire [size*width-1:0] inp_data_wire [3:0];
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| 40 |
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| 41 | reg [size*8-1:0] amp_data_reg, amp_data_next;
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| 42 | wire [size*8-1:0] amp_data_wire [2:0];
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| 43 |
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| 44 | reg [size*16-1:0] tau_data_reg, tau_data_next;
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| 45 | wire [size*16-1:0] tau_data_wire [2:0];
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| 46 |
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[113] | 47 | integer i;
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| 48 | genvar j;
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| 49 |
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| 50 | generate
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| 51 | for (j = 0; j < size; j = j + 1)
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| 52 | begin : INT_DATA
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[114] | 53 | assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(3*j+0)*width+width-1:(3*j+0)*width];
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| 54 | assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(3*j+1)*width+width-1:(3*j+1)*width];
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| 55 | assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(3*j+2)*width+width-1:(3*j+2)*width];
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| 56 | assign amp_data_wire[0][j*8+8-1:j*8] = amp_data[(3*j+0)*8+8-1:(3*j+0)*8];
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| 57 | assign amp_data_wire[1][j*8+8-1:j*8] = amp_data[(3*j+1)*8+8-1:(3*j+1)*8];
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| 58 | assign amp_data_wire[2][j*8+8-1:j*8] = amp_data[(3*j+2)*8+8-1:(3*j+2)*8];
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| 59 | assign tau_data_wire[0][j*16+16-1:j*16] = tau_data[(3*j+0)*16+16-1:(3*j+0)*16];
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| 60 | assign tau_data_wire[1][j*16+16-1:j*16] = tau_data[(3*j+1)*16+16-1:(3*j+1)*16];
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| 61 | assign tau_data_wire[2][j*16+16-1:j*16] = tau_data[(3*j+2)*16+16-1:(3*j+2)*16];
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[113] | 62 |
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[114] | 63 | lpm_mux #(
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| 64 | .lpm_size(3),
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| 65 | .lpm_type("LPM_MUX"),
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| 66 | .lpm_width(8),
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| 67 | .lpm_widths(2)) mux_unit_1 (
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| 68 | .sel(int_chan_next),
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| 69 | .data({
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| 70 | 2'd2, del_data[(3*j+2)*6+6-1:(3*j+2)*6],
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| 71 | 2'd1, del_data[(3*j+1)*6+6-1:(3*j+1)*6],
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| 72 | 2'd0, del_data[(3*j+0)*6+6-1:(3*j+0)*6]}),
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| 73 | .result(int_addr_wire));
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| 74 |
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[113] | 75 | lpm_add_sub #(
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[114] | 76 | .lpm_direction("SUB"),
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[113] | 77 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 78 | .lpm_representation("UNSIGNED"),
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| 79 | .lpm_type("LPM_ADD_SUB"),
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| 80 | .lpm_width(6)) add_unit_1 (
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[114] | 81 | .dataa(del_addr_reg),
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[113] | 82 | .datab(int_addr_wire[5:0]),
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| 83 | .result(del_addr_wire));
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| 84 |
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| 85 | lpm_add_sub #(
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| 86 | .lpm_direction("SUB"),
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| 87 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 88 | .lpm_representation("SIGNED"),
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| 89 | .lpm_type("LPM_ADD_SUB"),
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[114] | 90 | .lpm_width(width1)) sub_unit_1 (
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| 91 | .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}),
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| 92 | .datab({{(width1-width){1'b0}}, inp_data_wire[3][j*width+width-1:j*width]}),
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| 93 | .result(sub_data_wire[j*width1+width1-1:j*width1]));
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[113] | 94 |
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| 95 | lpm_add_sub #(
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| 96 | .lpm_direction("ADD"),
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| 97 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 98 | .lpm_representation("SIGNED"),
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| 99 | .lpm_type("LPM_ADD_SUB"),
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[114] | 100 | .lpm_width(width2)) acc_unit_1 (
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[117] | 101 | .dataa({{(width2-width1+1){sub_data_wire[j*width1+width1-1]}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),
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[114] | 102 | .datab(acc_data_reg[0][j*width2+width2-1:j*width2]),
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| 103 | .result(acc_data_wire[j*width2+width2-1:j*width2]));
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[113] | 104 |
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| 105 | lpm_mult #(
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| 106 | .lpm_hint("MAXIMIZE_SPEED=9"),
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| 107 | .lpm_representation("SIGNED"),
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| 108 | .lpm_type("LPM_MULT"),
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| 109 | .lpm_pipeline(3),
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[114] | 110 | .lpm_widtha(width1),
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| 111 | .lpm_widthb(17),
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| 112 | .lpm_widthp(widthr)) mult_unit_1 (
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[113] | 113 | .clock(clock),
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| 114 | .clken(int_wren_reg),
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[117] | 115 | .dataa(sub_data_wire[j*width1+width1-1:j*width1]),
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[114] | 116 | .datab({1'b0, tau_data_reg[j*16+16-1:j*16]}),
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| 117 | .result(mul_data_wire[0][j*widthr+widthr-1:j*widthr]));
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[113] | 118 |
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| 119 | lpm_mult #(
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| 120 | .lpm_hint("MAXIMIZE_SPEED=9"),
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[114] | 121 | .lpm_representation("UNSIGNED"),
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[113] | 122 | .lpm_type("LPM_MULT"),
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| 123 | .lpm_pipeline(3),
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[114] | 124 | .lpm_widtha(width2),
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| 125 | .lpm_widthb(8),
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[113] | 126 | .lpm_widthp(widthr)) mult_unit_2 (
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| 127 | .clock(clock),
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| 128 | .clken(int_wren_reg),
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[114] | 129 | .dataa(acc_data_reg[0][j*width2+width2-1:j*width2]),
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| 130 | .datab(amp_data_reg[j*8+8-1:j*8]),
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| 131 | .result(mul_data_wire[1][j*widthr+widthr-1:j*widthr]));
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[113] | 132 |
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| 133 | lpm_add_sub #(
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| 134 | .lpm_direction("ADD"),
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| 135 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 136 | .lpm_representation("SIGNED"),
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| 137 | .lpm_type("LPM_ADD_SUB"),
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| 138 | .lpm_width(widthr)) add_unit_2 (
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[117] | 139 | .dataa(mul_data_wire[0][j*widthr+widthr-1:j*widthr]),
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| 140 | .datab(mul_data_wire[1][j*widthr+widthr-1:j*widthr]),
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[114] | 141 | .result(out_data_wire[j*widthr+widthr-1:j*widthr]));
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[113] | 142 |
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[117] | 143 | /*
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| 144 | lpm_clshift #(
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| 145 | .lpm_shifttype("LOGICAL"),
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| 146 | .lpm_type("LPM_CLSHIFT"),
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| 147 | .lpm_width(64),
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| 148 | .lpm_widthdist(6)) shift_unit_1 (
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| 149 | .distance(distance),
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| 150 | .direction(sub_wire1),
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| 151 | .data(data),
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| 152 | .result(sub_wire0));
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| 153 | */
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[113] | 154 | end
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| 155 | endgenerate
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| 156 |
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| 157 |
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| 158 | altsyncram #(
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| 159 | .address_aclr_b("NONE"),
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| 160 | .address_reg_b("CLOCK0"),
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| 161 | .clock_enable_input_a("BYPASS"),
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| 162 | .clock_enable_input_b("BYPASS"),
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| 163 | .clock_enable_output_b("BYPASS"),
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| 164 | .intended_device_family("Cyclone III"),
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| 165 | .lpm_type("altsyncram"),
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| 166 | .numwords_a(256),
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| 167 | .numwords_b(256),
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| 168 | .operation_mode("DUAL_PORT"),
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| 169 | .outdata_aclr_b("NONE"),
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| 170 | .outdata_reg_b("CLOCK0"),
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| 171 | .power_up_uninitialized("FALSE"),
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| 172 | .read_during_write_mode_mixed_ports("DONT_CARE"),
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| 173 | .widthad_a(8),
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| 174 | .widthad_b(8),
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[114] | 175 | .width_a(size*width),
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| 176 | .width_b(size*width),
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[113] | 177 | .width_byteena_a(1)) ram_unit_1 (
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| 178 | .wren_a(int_wren_reg),
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| 179 | .clock0(clock),
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| 180 | .address_a(int_addr_reg),
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| 181 | .address_b({int_addr_wire[7:6], del_addr_wire}),
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[114] | 182 | .data_a(inp_data_reg[0]),
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| 183 | .q_b(inp_data_wire[3]),
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[113] | 184 | .aclr0(1'b0),
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| 185 | .aclr1(1'b0),
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| 186 | .addressstall_a(1'b0),
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| 187 | .addressstall_b(1'b0),
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| 188 | .byteena_a(1'b1),
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| 189 | .byteena_b(1'b1),
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| 190 | .clock1(1'b1),
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| 191 | .clocken0(1'b1),
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| 192 | .clocken1(1'b1),
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| 193 | .clocken2(1'b1),
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| 194 | .clocken3(1'b1),
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[114] | 195 | .data_b({(size*width){1'b1}}),
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[113] | 196 | .eccstatus(),
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| 197 | .q_a(),
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| 198 | .rden_a(1'b1),
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| 199 | .rden_b(1'b1),
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| 200 | .wren_b(1'b0));
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| 201 |
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| 202 | always @(posedge clock)
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| 203 | begin
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| 204 | if (reset)
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| 205 | begin
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| 206 | int_wren_reg <= 1'b1;
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| 207 | int_chan_reg <= 2'd0;
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| 208 | int_case_reg <= 3'd0;
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[114] | 209 | del_addr_reg <= 6'd0;
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[113] | 210 | int_addr_reg <= 8'd0;
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[114] | 211 | amp_data_reg <= 8'd0;
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| 212 | tau_data_reg <= 16'd0;
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| 213 | for(i = 0; i <= 2; i = i + 1)
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[113] | 214 | begin
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[114] | 215 | inp_data_reg[i] <= {(size*width){1'b0}};
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| 216 | out_data_reg[i] <= {(size*widthr){1'b0}};
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[113] | 217 | end
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[114] | 218 | for(i = 0; i <= 3; i = i + 1)
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[113] | 219 | begin
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[114] | 220 | acc_data_reg[i] <= {(size*width2){1'b0}};
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[113] | 221 | end
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| 222 | end
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| 223 | else
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| 224 | begin
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| 225 | int_wren_reg <= int_wren_next;
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| 226 | int_chan_reg <= int_chan_next;
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| 227 | int_case_reg <= int_case_next;
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[114] | 228 | del_addr_reg <= del_addr_next;
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[113] | 229 | int_addr_reg <= int_addr_next;
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[114] | 230 | amp_data_reg <= amp_data_next;
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| 231 | tau_data_reg <= tau_data_next;
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| 232 | for(i = 0; i <= 2; i = i + 1)
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[113] | 233 | begin
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[114] | 234 | inp_data_reg[i] <= inp_data_next[i];
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| 235 | out_data_reg[i] <= out_data_next[i];
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| 236 | end
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| 237 | for(i = 0; i <= 3; i = i + 1)
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| 238 | begin
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[113] | 239 | acc_data_reg[i] <= acc_data_next[i];
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[114] | 240 | end
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[113] | 241 | end
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| 242 | end
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| 243 |
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| 244 | always @*
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| 245 | begin
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| 246 | int_wren_next = int_wren_reg;
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| 247 | int_chan_next = int_chan_reg;
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| 248 | int_case_next = int_case_reg;
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[114] | 249 | del_addr_next = del_addr_reg;
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[113] | 250 | int_addr_next = int_addr_reg;
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[114] | 251 | amp_data_next = amp_data_reg;
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| 252 | tau_data_next = tau_data_reg;
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| 253 | for(i = 0; i <= 2; i = i + 1)
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[113] | 254 | begin
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[114] | 255 | inp_data_next[i] = inp_data_reg[i];
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| 256 | out_data_next[i] = out_data_reg[i];
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| 257 | end
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| 258 | for(i = 0; i <= 3; i = i + 1)
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| 259 | begin
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[113] | 260 | acc_data_next[i] = acc_data_reg[i];
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[114] | 261 | end
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[113] | 262 |
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| 263 | case (int_case_reg)
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| 264 | 0:
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| 265 | begin
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| 266 | // write zeros
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| 267 | int_wren_next = 1'b1;
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[114] | 268 | del_addr_next = 6'd0;
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[113] | 269 | int_addr_next = 8'd0;
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[114] | 270 | amp_data_next = 8'd0;
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| 271 | tau_data_next = 16'd0;
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| 272 | for(i = 0; i <= 2; i = i + 1)
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[113] | 273 | begin
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[114] | 274 | inp_data_next[i] = {(size*width){1'b0}};
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| 275 | out_data_next[i] = {(size*widthr){1'b0}};
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| 276 | end
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| 277 | for(i = 0; i <= 3; i = i + 1)
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[113] | 278 | begin
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[114] | 279 | acc_data_next[i] = {(size*width2){1'b0}};
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| 280 | end
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| 281 |
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[113] | 282 | int_case_next = 3'd1;
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| 283 | end
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| 284 | 1:
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| 285 | begin
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| 286 | // write zeros
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| 287 | int_addr_next = int_addr_reg + 8'd1;
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| 288 | if (&int_addr_reg)
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| 289 | begin
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| 290 | int_wren_next = 1'b0;
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| 291 | int_chan_next = 2'd0;
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| 292 | int_case_next = 3'd2;
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| 293 | end
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| 294 | end
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| 295 | 2: // frame
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| 296 | begin
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| 297 | if (frame)
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| 298 | begin
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| 299 | int_wren_next = 1'b1;
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| 300 |
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| 301 | int_addr_next[7:6] = 2'd0;
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| 302 |
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| 303 | // set read addr for 2nd pipeline
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| 304 | int_chan_next = 2'd1;
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| 305 |
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| 306 | // register input data for 2nd and 3rd sums
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[114] | 307 | inp_data_next[1] = inp_data_wire[1];
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| 308 | inp_data_next[2] = inp_data_wire[2];
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[113] | 309 |
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| 310 | // prepare registers for 1st sum
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[114] | 311 | inp_data_next[0] = inp_data_wire[0];
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| 312 | acc_data_next[0] = acc_data_reg[1];
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| 313 |
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| 314 | tau_data_next = tau_data_wire[0];
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| 315 | amp_data_next = amp_data_wire[0];
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| 316 |
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[113] | 317 | int_case_next = 3'd3;
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| 318 | end
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| 319 |
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| 320 | end
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| 321 | 3: // 1st sum
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| 322 | begin
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| 323 | int_addr_next[7:6] = 2'd1;
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| 324 |
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| 325 | // set read addr for 3rd pipeline
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| 326 | int_chan_next = 2'd2;
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| 327 |
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| 328 | // prepare registers for 2nd sum
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[114] | 329 | inp_data_next[0] = inp_data_reg[1];
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| 330 | acc_data_next[0] = acc_data_reg[2];
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| 331 |
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| 332 | tau_data_next = tau_data_wire[1];
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| 333 | amp_data_next = amp_data_wire[1];
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| 334 |
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[113] | 335 | // register 1st sum
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[114] | 336 | acc_data_next[1] = acc_data_wire;
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| 337 | out_data_next[0] = out_data_wire;
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[113] | 338 |
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| 339 | int_case_next = 3'd4;
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| 340 | end
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| 341 | 4: // 2nd sum
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| 342 | begin
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| 343 | int_addr_next[7:6] = 2'd2;
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| 344 |
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| 345 | // prepare registers for 3rd sum
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[114] | 346 | inp_data_next[0] = inp_data_reg[2];
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| 347 | acc_data_next[0] = acc_data_reg[3];
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| 348 |
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| 349 | tau_data_next = tau_data_wire[2];
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| 350 | amp_data_next = amp_data_wire[2];
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[113] | 351 |
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| 352 | // register 2nd sum
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[114] | 353 | acc_data_next[2] = acc_data_wire;
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| 354 | out_data_next[1] = out_data_wire;
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[113] | 355 |
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[114] | 356 | del_addr_next = del_addr_reg + 6'd1;
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| 357 |
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[113] | 358 | int_case_next = 3'd5;
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| 359 | end
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| 360 | 5: // 3rd sum
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| 361 | begin
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| 362 | int_wren_next = 1'b0;
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| 363 |
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| 364 | // set read addr for 1st pipeline
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| 365 | int_chan_next = 2'd0;
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| 366 |
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| 367 | // register 3rd sum
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[114] | 368 | acc_data_next[3] = acc_data_wire;
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| 369 | out_data_next[2] = out_data_wire;
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[113] | 370 |
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[114] | 371 | int_addr_next[5:0] = del_addr_reg;
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[113] | 372 |
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| 373 | int_case_next = 3'd2;
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| 374 | end
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| 375 | default:
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| 376 | begin
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| 377 | int_case_next = 3'd0;
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| 378 | end
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| 379 | endcase
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| 380 | end
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| 381 |
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[114] | 382 | assign out_data = {out_data_reg[2], out_data_reg[1], out_data_reg[0]};
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[113] | 383 |
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| 384 | endmodule
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