source: sandbox/MultiChannelUSB/cic_pipeline.v@ 128

Last change on this file since 128 was 107, checked in by demin, 14 years ago

Starting to test signal shaping algorithms
File size: 2.3 KB
Line 
1module cic_pipeline
2 #(
3 parameter width = 192
4 )
5 (
6 input wire clock,
7 input wire [width-1:0] data,
8 input wire [7:0] rdaddress_a,
9 input wire [7:0] rdaddress_b,
10 input wire [7:0] wraddress,
11 input wire wren,
12 output wire [width-1:0] qa,
13 output wire [width-1:0] qb
14 );
15
16 altsyncram #(
17 .address_aclr_b("NONE"),
18 .address_reg_b("CLOCK0"),
19 .clock_enable_input_a("BYPASS"),
20 .clock_enable_input_b("BYPASS"),
21 .clock_enable_output_b("BYPASS"),
22 .intended_device_family("Cyclone III"),
23 .lpm_type("altsyncram"),
24 .numwords_a(256),
25 .numwords_b(256),
26 .operation_mode("DUAL_PORT"),
27 .outdata_aclr_b("NONE"),
28 .outdata_reg_b("CLOCK0"),
29 .power_up_uninitialized("FALSE"),
30 .read_during_write_mode_mixed_ports("DONT_CARE"),
31 .widthad_a(8),
32 .widthad_b(8),
33 .width_a(width),
34 .width_b(width),
35 .width_byteena_a(1)) ram_unit_a(
36 .wren_a(wren),
37 .clock0(clock),
38 .address_a(wraddress),
39 .address_b(rdaddress_a),
40 .data_a(data),
41 .q_b(qa),
42 .aclr0(1'b0),
43 .aclr1(1'b0),
44 .addressstall_a(1'b0),
45 .addressstall_b(1'b0),
46 .byteena_a(1'b1),
47 .byteena_b(1'b1),
48 .clock1(1'b1),
49 .clocken0(1'b1),
50 .clocken1(1'b1),
51 .clocken2(1'b1),
52 .clocken3(1'b1),
53 .data_b({width{1'b1}}),
54 .eccstatus(),
55 .q_a(),
56 .rden_a(1'b1),
57 .rden_b(1'b1),
58 .wren_b(1'b0));
59
60 altsyncram #(
61 .address_aclr_b("NONE"),
62 .address_reg_b("CLOCK0"),
63 .clock_enable_input_a("BYPASS"),
64 .clock_enable_input_b("BYPASS"),
65 .clock_enable_output_b("BYPASS"),
66 .intended_device_family("Cyclone III"),
67 .lpm_type("altsyncram"),
68 .numwords_a(256),
69 .numwords_b(256),
70 .operation_mode("DUAL_PORT"),
71 .outdata_aclr_b("NONE"),
72 .outdata_reg_b("CLOCK0"),
73 .power_up_uninitialized("FALSE"),
74 .read_during_write_mode_mixed_ports("DONT_CARE"),
75 .widthad_a(8),
76 .widthad_b(8),
77 .width_a(width),
78 .width_b(width),
79 .width_byteena_a(1)) ram_unit_b(
80 .wren_a(wren),
81 .clock0(clock),
82 .address_a(wraddress),
83 .address_b(rdaddress_b),
84 .data_a(data),
85 .q_b(qb),
86 .aclr0(1'b0),
87 .aclr1(1'b0),
88 .addressstall_a(1'b0),
89 .addressstall_b(1'b0),
90 .byteena_a(1'b1),
91 .byteena_b(1'b1),
92 .clock1(1'b1),
93 .clocken0(1'b1),
94 .clocken1(1'b1),
95 .clocken2(1'b1),
96 .clocken3(1'b1),
97 .data_b({width{1'b1}}),
98 .eccstatus(),
99 .q_a(),
100 .rden_a(1'b1),
101 .rden_b(1'b1),
102 .wren_b(1'b0));
103
104endmodule
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