1 | module cic_filter
|
---|
2 | #(
|
---|
3 | parameter size = 3, // number of channels
|
---|
4 | parameter width = 12 // bit width of the input data (unsigned)
|
---|
5 | )
|
---|
6 | (
|
---|
7 | input wire clock, frame, reset,
|
---|
8 | input wire [size*width-1:0] inp_data,
|
---|
9 | output wire [size*widthr-1:0] out_data,
|
---|
10 | output wire [size*widthr-1:0] out_data2,
|
---|
11 | output wire [size*widthr-1:0] out_data3
|
---|
12 | );
|
---|
13 |
|
---|
14 | localparam widthr = width + 13;
|
---|
15 |
|
---|
16 | /*
|
---|
17 | 4-bit LFSR with additional bits to keep track of previous values
|
---|
18 | */
|
---|
19 | reg [15:0] int_lfsr_reg, int_lfsr_next;
|
---|
20 |
|
---|
21 | reg int_wren_reg, int_wren_next;
|
---|
22 | reg [1:0] int_chan_reg, int_chan_next;
|
---|
23 | reg [2:0] int_case_reg, int_case_next;
|
---|
24 | reg [7:0] int_addr_reg, int_addr_next;
|
---|
25 |
|
---|
26 | wire [9:0] int_addr_wire;
|
---|
27 |
|
---|
28 | reg [size*widthr-1:0] acc_data_reg [2:0], acc_data_next [2:0];
|
---|
29 | reg [size*widthr-1:0] int_data_reg [5:0], int_data_next [5:0];
|
---|
30 |
|
---|
31 | wire [size*widthr-1:0] acc_data_wire [2:0], del_data_wire [1:0];
|
---|
32 |
|
---|
33 |
|
---|
34 | integer i;
|
---|
35 | genvar j;
|
---|
36 |
|
---|
37 | generate
|
---|
38 | for (j = 0; j < size; j = j + 1)
|
---|
39 | begin : INT_DATA
|
---|
40 | assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
|
---|
41 |
|
---|
42 | // -2*del_data_1 + del_data_2 + inp_data + result
|
---|
43 | parallel_add #(
|
---|
44 | .msw_subtract("YES"),
|
---|
45 | .representation("SIGNED"),
|
---|
46 | .result_alignment("LSB"),
|
---|
47 | .shift(0),
|
---|
48 | .size(4),
|
---|
49 | .width(widthr),
|
---|
50 | .widthr(widthr)) acc_unit_1 (
|
---|
51 | .data({
|
---|
52 | {del_data_wire[0][j*widthr+widthr-1],del_data_wire[0][j*widthr+widthr-3:j*widthr], 1'b0},
|
---|
53 | {del_data_wire[1][j*widthr+widthr-1:j*widthr]},
|
---|
54 | {acc_data_reg[0][j*widthr+widthr-1:j*widthr]},
|
---|
55 | {acc_data_reg[1][j*widthr+widthr-1:j*widthr]}}),
|
---|
56 | .result(acc_data_wire[1][j*widthr+widthr-1:j*widthr]));
|
---|
57 |
|
---|
58 | parallel_add #(
|
---|
59 | .msw_subtract("NO"),
|
---|
60 | .representation("SIGNED"),
|
---|
61 | .result_alignment("LSB"),
|
---|
62 | .shift(0),
|
---|
63 | .size(2),
|
---|
64 | .width(widthr),
|
---|
65 | .widthr(widthr)) acc_unit_2 (
|
---|
66 | .data({
|
---|
67 | {acc_data_reg[1][j*widthr+widthr-1:j*widthr]},
|
---|
68 | {acc_data_reg[2][j*widthr+widthr-1:j*widthr]}}),
|
---|
69 | .result(acc_data_wire[2][j*widthr+widthr-1:j*widthr]));
|
---|
70 |
|
---|
71 | end
|
---|
72 | endgenerate
|
---|
73 |
|
---|
74 | cic_pipeline #(
|
---|
75 | .width(size*widthr)) cic_pipeline_unit (
|
---|
76 | .clock(clock),
|
---|
77 | .data(acc_data_reg[0]),
|
---|
78 | .rdaddress_a({int_addr_wire[9:8], int_addr_wire[3:0]}),
|
---|
79 | .rdaddress_b({int_addr_wire[9:8], int_addr_wire[7:4]}),
|
---|
80 | .wraddress(int_addr_reg),
|
---|
81 | .wren(int_wren_reg),
|
---|
82 | .qa(del_data_wire[0]),
|
---|
83 | .qb(del_data_wire[1]));
|
---|
84 |
|
---|
85 | lpm_mux #(
|
---|
86 | .lpm_size(3),
|
---|
87 | .lpm_type("LPM_MUX"),
|
---|
88 | .lpm_width(10),
|
---|
89 | .lpm_widths(2)) mux_unit_1 (
|
---|
90 | .sel(int_chan_next),
|
---|
91 | .data({
|
---|
92 | 2'd2, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5],
|
---|
93 | 2'd1, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4],
|
---|
94 | 2'd0, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3]}),
|
---|
95 | .result(int_addr_wire));
|
---|
96 |
|
---|
97 | always @(posedge clock)
|
---|
98 | begin
|
---|
99 | if (reset)
|
---|
100 | begin
|
---|
101 | int_wren_reg <= 1'b1;
|
---|
102 | int_chan_reg <= 2'd0;
|
---|
103 | int_case_reg <= 3'd0;
|
---|
104 | int_addr_reg <= 8'd0;
|
---|
105 | for(i = 0; i <= 2; i = i + 1)
|
---|
106 | begin
|
---|
107 | acc_data_reg[i] <= {(size*widthr){1'b0}};
|
---|
108 | end
|
---|
109 | for(i = 0; i <= 5; i = i + 1)
|
---|
110 | begin
|
---|
111 | int_data_reg[i] <= {(size*widthr){1'b0}};
|
---|
112 | end
|
---|
113 | int_lfsr_reg <= 16'd0;
|
---|
114 | end
|
---|
115 | else
|
---|
116 | begin
|
---|
117 | int_wren_reg <= int_wren_next;
|
---|
118 | int_chan_reg <= int_chan_next;
|
---|
119 | int_case_reg <= int_case_next;
|
---|
120 | int_addr_reg <= int_addr_next;
|
---|
121 | for(i = 0; i <= 2; i = i + 1)
|
---|
122 | begin
|
---|
123 | acc_data_reg[i] <= acc_data_next[i];
|
---|
124 | end
|
---|
125 | for(i = 0; i <= 5; i = i + 1)
|
---|
126 | begin
|
---|
127 | int_data_reg[i] <= int_data_next[i];
|
---|
128 | end
|
---|
129 | int_lfsr_reg <= int_lfsr_next;
|
---|
130 | end
|
---|
131 | end
|
---|
132 |
|
---|
133 | always @*
|
---|
134 | begin
|
---|
135 | int_wren_next = int_wren_reg;
|
---|
136 | int_chan_next = int_chan_reg;
|
---|
137 | int_case_next = int_case_reg;
|
---|
138 | int_addr_next = int_addr_reg;
|
---|
139 | for(i = 0; i <= 2; i = i + 1)
|
---|
140 | begin
|
---|
141 | acc_data_next[i] = acc_data_reg[i];
|
---|
142 | end
|
---|
143 | for(i = 0; i <= 5; i = i + 1)
|
---|
144 | begin
|
---|
145 | int_data_next[i] = int_data_reg[i];
|
---|
146 | end
|
---|
147 | int_lfsr_next = int_lfsr_reg;
|
---|
148 |
|
---|
149 | case (int_case_reg)
|
---|
150 | 0:
|
---|
151 | begin
|
---|
152 | // write zeros
|
---|
153 | int_wren_next = 1'b1;
|
---|
154 | int_addr_next = 8'd0;
|
---|
155 | for(i = 0; i <= 2; i = i + 1)
|
---|
156 | begin
|
---|
157 | acc_data_next[i] = {(size*widthr){1'b0}};
|
---|
158 | end
|
---|
159 | for(i = 0; i <= 5; i = i + 1)
|
---|
160 | begin
|
---|
161 | int_data_next[i] = {(size*widthr){1'b0}};
|
---|
162 | end
|
---|
163 | int_case_next = 3'd1;
|
---|
164 | end
|
---|
165 | 1:
|
---|
166 | begin
|
---|
167 | // write zeros
|
---|
168 | int_addr_next = int_addr_reg + 8'd1;
|
---|
169 | if (&int_addr_reg)
|
---|
170 | begin
|
---|
171 | int_wren_next = 1'b0;
|
---|
172 | int_chan_next = 2'd0;
|
---|
173 | int_lfsr_next = 16'h7650;
|
---|
174 | int_case_next = 3'd2;
|
---|
175 | end
|
---|
176 | end
|
---|
177 | 2: // frame
|
---|
178 | begin
|
---|
179 | if (frame)
|
---|
180 | begin
|
---|
181 | int_wren_next = 1'b1;
|
---|
182 |
|
---|
183 | int_addr_next = {4'd0, int_lfsr_reg[3:0]};
|
---|
184 |
|
---|
185 | // set read addr for 2nd pipeline
|
---|
186 | int_chan_next = 2'd1;
|
---|
187 |
|
---|
188 | // prepare registers for 1st sum
|
---|
189 | acc_data_next[0] = acc_data_wire[0];
|
---|
190 | acc_data_next[1] = int_data_reg[0];
|
---|
191 | acc_data_next[2] = int_data_reg[1];
|
---|
192 |
|
---|
193 | int_case_next = 3'd3;
|
---|
194 | end
|
---|
195 |
|
---|
196 | end
|
---|
197 | 3: // 1st sum
|
---|
198 | begin
|
---|
199 | int_addr_next = {4'd1, int_lfsr_reg[3:0]};
|
---|
200 |
|
---|
201 | // set read addr for 3rd pipeline
|
---|
202 | int_chan_next = 2'd2;
|
---|
203 |
|
---|
204 | // prepare registers for 2nd sum
|
---|
205 | acc_data_next[0] = int_data_reg[1];
|
---|
206 | acc_data_next[1] = int_data_reg[2];
|
---|
207 | acc_data_next[2] = int_data_reg[3];
|
---|
208 |
|
---|
209 | // register 1st sum
|
---|
210 | int_data_next[0] = acc_data_wire[1];
|
---|
211 | int_data_next[1] = acc_data_wire[2];
|
---|
212 |
|
---|
213 | int_case_next = 3'd4;
|
---|
214 | end
|
---|
215 | 4: // 2nd sum
|
---|
216 | begin
|
---|
217 | int_addr_next = {4'd2, int_lfsr_reg[3:0]};
|
---|
218 |
|
---|
219 | // prepare registers for 3rd sum
|
---|
220 | acc_data_next[0] = int_data_reg[3];
|
---|
221 | acc_data_next[1] = int_data_reg[4];
|
---|
222 | acc_data_next[2] = int_data_reg[5];
|
---|
223 |
|
---|
224 | // register 2nd sum
|
---|
225 | int_data_next[2] = acc_data_wire[1];
|
---|
226 | int_data_next[3] = acc_data_wire[2];
|
---|
227 |
|
---|
228 | int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]};
|
---|
229 |
|
---|
230 | int_case_next = 3'd5;
|
---|
231 | end
|
---|
232 | 5: // 3rd sum
|
---|
233 | begin
|
---|
234 | int_wren_next = 1'b0;
|
---|
235 |
|
---|
236 | // set read addr for 1st pipeline
|
---|
237 | int_chan_next = 2'd0;
|
---|
238 |
|
---|
239 | // register 3rd sum
|
---|
240 | int_data_next[4] = acc_data_wire[1];
|
---|
241 | int_data_next[5] = acc_data_wire[2];
|
---|
242 |
|
---|
243 | int_case_next = 3'd2;
|
---|
244 | end
|
---|
245 | default:
|
---|
246 | begin
|
---|
247 | int_case_next = 3'd0;
|
---|
248 | end
|
---|
249 | endcase
|
---|
250 | end
|
---|
251 |
|
---|
252 | assign out_data = int_data_reg[1];
|
---|
253 | assign out_data2 = int_data_reg[3];
|
---|
254 | assign out_data3 = int_data_reg[5];
|
---|
255 |
|
---|
256 | endmodule
|
---|