[108] | 1 | module cic_filter
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[107] | 2 | #(
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| 3 | parameter size = 3, // number of channels
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| 4 | parameter width = 12 // bit width of the input data (unsigned)
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| 5 | )
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| 6 | (
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| 7 | input wire clock, frame, reset,
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| 8 | input wire [size*width-1:0] inp_data,
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| 9 | output wire [size*widthr-1:0] out_data,
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| 10 | output wire [size*widthr-1:0] out_data2,
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| 11 | output wire [size*widthr-1:0] out_data3
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| 12 | );
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| 13 |
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[123] | 14 | localparam widthr = width + 16;
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[107] | 15 | /*
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| 16 | 4-bit LFSR with additional bits to keep track of previous values
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| 17 | */
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| 18 | reg [15:0] int_lfsr_reg, int_lfsr_next;
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| 19 |
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| 20 | reg int_wren_reg, int_wren_next;
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[122] | 21 | reg int_flag_reg, int_flag_next;
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[107] | 22 | reg [1:0] int_chan_reg, int_chan_next;
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| 23 | reg [2:0] int_case_reg, int_case_next;
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| 24 | reg [7:0] int_addr_reg, int_addr_next;
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| 25 |
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| 26 | wire [9:0] int_addr_wire;
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| 27 |
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[121] | 28 | reg [size*widthr-1:0] acc_data_reg [3:0], acc_data_next [3:0];
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[122] | 29 | reg [size*widthr-1:0] int_data_reg [12:0], int_data_next [12:0];
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[107] | 30 |
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[121] | 31 | wire [size*widthr-1:0] acc_data_wire [3:0], del_data_wire [1:0];
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[107] | 32 |
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| 33 | integer i;
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| 34 | genvar j;
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| 35 |
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| 36 | generate
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| 37 | for (j = 0; j < size; j = j + 1)
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| 38 | begin : INT_DATA
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| 39 | assign acc_data_wire[0][j*widthr+widthr-1:j*widthr] = {{(widthr-width){1'b0}}, inp_data[j*width+width-1:j*width]};
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| 40 |
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| 41 | // -2*del_data_1 + del_data_2 + inp_data + result
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[119] | 42 |
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[121] | 43 | assign acc_data_wire[1][j*widthr+widthr-1:j*widthr] =
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| 44 | acc_data_reg[0][j*widthr+widthr-1:j*widthr]
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| 45 | + del_data_wire[1][j*widthr+widthr-1:j*widthr]
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| 46 | - {del_data_wire[0][j*widthr+widthr-1],del_data_wire[0][j*widthr+widthr-3:j*widthr], 1'b0};
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[119] | 47 |
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[121] | 48 | assign acc_data_wire[2][j*widthr+widthr-1:j*widthr] =
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| 49 | acc_data_reg[1][j*widthr+widthr-1:j*widthr]
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| 50 | + acc_data_reg[2][j*widthr+widthr-1:j*widthr];
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[119] | 51 |
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[121] | 52 | assign acc_data_wire[3][j*widthr+widthr-1:j*widthr] =
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| 53 | acc_data_reg[2][j*widthr+widthr-1:j*widthr]
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| 54 | + acc_data_reg[3][j*widthr+widthr-1:j*widthr];
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[107] | 55 |
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| 56 | end
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| 57 | endgenerate
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| 58 |
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| 59 | cic_pipeline #(
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| 60 | .width(size*widthr)) cic_pipeline_unit (
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| 61 | .clock(clock),
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| 62 | .data(acc_data_reg[0]),
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| 63 | .rdaddress_a({int_addr_wire[9:8], int_addr_wire[3:0]}),
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| 64 | .rdaddress_b({int_addr_wire[9:8], int_addr_wire[7:4]}),
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| 65 | .wraddress(int_addr_reg),
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| 66 | .wren(int_wren_reg),
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| 67 | .qa(del_data_wire[0]),
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| 68 | .qb(del_data_wire[1]));
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| 69 |
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| 70 | lpm_mux #(
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[122] | 71 | .lpm_size(4),
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[107] | 72 | .lpm_type("LPM_MUX"),
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| 73 | .lpm_width(10),
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| 74 | .lpm_widths(2)) mux_unit_1 (
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| 75 | .sel(int_chan_next),
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| 76 | .data({
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[123] | 77 | 2'd3, int_lfsr_reg[2*5+3:2*5], int_lfsr_reg[5+3:5],
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| 78 | 2'd2, int_lfsr_reg[2*4+3:2*4], int_lfsr_reg[4+3:4],
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| 79 | 2'd1, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3],
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[107] | 80 | 2'd0, int_lfsr_reg[2*3+3:2*3], int_lfsr_reg[3+3:3]}),
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[123] | 81 | .result(int_addr_wire));
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[107] | 82 |
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| 83 | always @(posedge clock)
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| 84 | begin
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| 85 | if (reset)
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| 86 | begin
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| 87 | int_wren_reg <= 1'b1;
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[122] | 88 | int_flag_reg <= 1'b0;
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[107] | 89 | int_chan_reg <= 2'd0;
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| 90 | int_case_reg <= 3'd0;
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| 91 | int_addr_reg <= 8'd0;
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[121] | 92 | for(i = 0; i <= 3; i = i + 1)
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[107] | 93 | begin
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| 94 | acc_data_reg[i] <= {(size*widthr){1'b0}};
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| 95 | end
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[122] | 96 | for(i = 0; i <= 12; i = i + 1)
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[107] | 97 | begin
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| 98 | int_data_reg[i] <= {(size*widthr){1'b0}};
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| 99 | end
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| 100 | int_lfsr_reg <= 16'd0;
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| 101 | end
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| 102 | else
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| 103 | begin
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| 104 | int_wren_reg <= int_wren_next;
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[122] | 105 | int_flag_reg <= int_flag_next;
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[107] | 106 | int_chan_reg <= int_chan_next;
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| 107 | int_case_reg <= int_case_next;
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| 108 | int_addr_reg <= int_addr_next;
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[121] | 109 | for(i = 0; i <= 3; i = i + 1)
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[107] | 110 | begin
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| 111 | acc_data_reg[i] <= acc_data_next[i];
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| 112 | end
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[122] | 113 | for(i = 0; i <= 12; i = i + 1)
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[107] | 114 | begin
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| 115 | int_data_reg[i] <= int_data_next[i];
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| 116 | end
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| 117 | int_lfsr_reg <= int_lfsr_next;
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| 118 | end
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| 119 | end
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| 120 |
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| 121 | always @*
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| 122 | begin
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| 123 | int_wren_next = int_wren_reg;
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[122] | 124 | int_flag_next = int_flag_reg;
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[107] | 125 | int_chan_next = int_chan_reg;
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| 126 | int_case_next = int_case_reg;
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| 127 | int_addr_next = int_addr_reg;
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[121] | 128 | for(i = 0; i <= 3; i = i + 1)
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[107] | 129 | begin
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| 130 | acc_data_next[i] = acc_data_reg[i];
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| 131 | end
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[122] | 132 | for(i = 0; i <= 12; i = i + 1)
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[107] | 133 | begin
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| 134 | int_data_next[i] = int_data_reg[i];
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| 135 | end
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| 136 | int_lfsr_next = int_lfsr_reg;
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| 137 |
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| 138 | case (int_case_reg)
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| 139 | 0:
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| 140 | begin
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| 141 | // write zeros
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| 142 | int_wren_next = 1'b1;
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| 143 | int_addr_next = 8'd0;
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[121] | 144 | for(i = 0; i <= 3; i = i + 1)
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[107] | 145 | begin
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| 146 | acc_data_next[i] = {(size*widthr){1'b0}};
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| 147 | end
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[122] | 148 | for(i = 0; i <= 12; i = i + 1)
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[107] | 149 | begin
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| 150 | int_data_next[i] = {(size*widthr){1'b0}};
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| 151 | end
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| 152 | int_case_next = 3'd1;
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| 153 | end
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| 154 | 1:
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| 155 | begin
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| 156 | // write zeros
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| 157 | int_addr_next = int_addr_reg + 8'd1;
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| 158 | if (&int_addr_reg)
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| 159 | begin
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| 160 | int_wren_next = 1'b0;
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[122] | 161 | int_flag_next = 1'b0;
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[107] | 162 | int_chan_next = 2'd0;
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| 163 | int_lfsr_next = 16'h7650;
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| 164 | int_case_next = 3'd2;
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| 165 | end
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| 166 | end
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| 167 | 2: // frame
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| 168 | begin
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[122] | 169 | int_flag_next = 1'b0;
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[107] | 170 | if (frame)
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| 171 | begin
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| 172 | int_wren_next = 1'b1;
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| 173 |
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| 174 | int_addr_next = {4'd0, int_lfsr_reg[3:0]};
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| 175 |
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| 176 | // set read addr for 2nd pipeline
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| 177 | int_chan_next = 2'd1;
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| 178 |
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| 179 | // prepare registers for 1st sum
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| 180 | acc_data_next[0] = acc_data_wire[0];
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| 181 | acc_data_next[1] = int_data_reg[0];
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| 182 | acc_data_next[2] = int_data_reg[1];
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[121] | 183 | acc_data_next[3] = int_data_reg[2];
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[107] | 184 |
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| 185 | int_case_next = 3'd3;
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| 186 | end
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[122] | 187 | if (int_flag_reg) // register 4th sum
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| 188 | begin
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| 189 | // register 4th sum
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| 190 | int_data_next[9] = acc_data_wire[1];
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| 191 | int_data_next[10] = acc_data_wire[2];
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| 192 | int_data_next[11] = acc_data_wire[3];
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| 193 | end
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[107] | 194 | end
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| 195 | 3: // 1st sum
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| 196 | begin
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| 197 | int_addr_next = {4'd1, int_lfsr_reg[3:0]};
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| 198 |
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| 199 | // set read addr for 3rd pipeline
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| 200 | int_chan_next = 2'd2;
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| 201 |
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| 202 | // prepare registers for 2nd sum
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[121] | 203 | acc_data_next[0] = int_data_reg[2];
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| 204 | acc_data_next[1] = int_data_reg[3];
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| 205 | acc_data_next[2] = int_data_reg[4];
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| 206 | acc_data_next[3] = int_data_reg[5];
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[107] | 207 |
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| 208 | // register 1st sum
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| 209 | int_data_next[0] = acc_data_wire[1];
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| 210 | int_data_next[1] = acc_data_wire[2];
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[121] | 211 | int_data_next[2] = acc_data_wire[3];
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[107] | 212 |
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| 213 | int_case_next = 3'd4;
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| 214 | end
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| 215 | 4: // 2nd sum
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| 216 | begin
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| 217 | int_addr_next = {4'd2, int_lfsr_reg[3:0]};
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| 218 |
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[122] | 219 | // set read addr for 4th pipeline
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| 220 | int_chan_next = 2'd3;
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| 221 |
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[107] | 222 | // prepare registers for 3rd sum
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[121] | 223 | acc_data_next[0] = int_data_reg[5];
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| 224 | acc_data_next[1] = int_data_reg[6];
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| 225 | acc_data_next[2] = int_data_reg[7];
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| 226 | acc_data_next[3] = int_data_reg[8];
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[107] | 227 |
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| 228 | // register 2nd sum
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[121] | 229 | int_data_next[3] = acc_data_wire[1];
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| 230 | int_data_next[4] = acc_data_wire[2];
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| 231 | int_data_next[5] = acc_data_wire[3];
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[107] | 232 |
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| 233 | int_lfsr_next = {int_lfsr_reg[14:0], int_lfsr_reg[2] ~^ int_lfsr_reg[3]};
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| 234 |
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| 235 | int_case_next = 3'd5;
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| 236 | end
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| 237 | 5: // 3rd sum
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| 238 | begin
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[122] | 239 | int_flag_next = 1'b1;
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[107] | 240 |
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[122] | 241 | int_addr_next = {4'd3, int_lfsr_reg[4:1]};
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| 242 |
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[107] | 243 | // set read addr for 1st pipeline
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| 244 | int_chan_next = 2'd0;
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| 245 |
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[122] | 246 | // prepare registers for 4th sum
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| 247 | acc_data_next[0] = int_data_reg[8];
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| 248 | acc_data_next[1] = int_data_reg[9];
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| 249 | acc_data_next[2] = int_data_reg[10];
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| 250 | acc_data_next[3] = int_data_reg[11];
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| 251 |
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[107] | 252 | // register 3rd sum
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[121] | 253 | int_data_next[6] = acc_data_wire[1];
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| 254 | int_data_next[7] = acc_data_wire[2];
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| 255 | int_data_next[8] = acc_data_wire[3];
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[122] | 256 |
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| 257 | // register 4th output
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| 258 | int_data_next[12] = int_data_reg[11];
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[107] | 259 |
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| 260 | int_case_next = 3'd2;
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| 261 | end
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| 262 | default:
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| 263 | begin
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| 264 | int_case_next = 3'd0;
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| 265 | end
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| 266 | endcase
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| 267 | end
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| 268 |
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[122] | 269 | assign out_data = int_data_reg[5];
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| 270 | assign out_data2 = int_data_reg[8];
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| 271 | assign out_data3 = int_data_reg[12];
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[107] | 272 |
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| 273 | endmodule
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