[115] | 1 | module average
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| 2 | #(
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| 3 | parameter size = 1, // number of channels
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| 4 | parameter width = 16 // bit width of the input data
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| 5 | )
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| 6 | (
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| 7 | input wire clock, frame, reset,
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| 8 | input wire [3*size*6-1:0] del_data,
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| 9 | input wire [3*size*width-1:0] inp_data,
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| 10 | output wire [3*size*width1-1:0] out_data
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| 11 | );
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| 12 |
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| 13 |
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| 14 | localparam width1 = width + 6 + 1;
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| 15 |
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| 16 | reg int_wren_reg, int_wren_next;
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| 17 | reg [1:0] int_chan_reg, int_chan_next;
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| 18 | reg [2:0] int_case_reg, int_case_next;
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| 19 | reg [7:0] int_addr_reg, int_addr_next;
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| 20 |
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| 21 | reg [5:0] del_addr_reg, del_addr_next;
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| 22 | wire [5:0] del_addr_wire;
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| 23 | wire [7:0] int_addr_wire;
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| 24 |
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| 25 | reg [size*width-1:0] inp_data_reg [2:0], inp_data_next [2:0];
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| 26 | wire [size*width-1:0] inp_data_wire [3:0];
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| 27 |
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| 28 | reg [size*width1-1:0] out_data_reg [2:0], out_data_next [2:0];
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| 29 | wire [size*width1-1:0] out_data_wire;
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| 30 |
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| 31 | reg [size*width1-1:0] acc_data_reg [3:0], acc_data_next [3:0];
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| 32 | wire [size*width1-1:0] acc_data_wire;
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| 33 |
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| 34 | reg [size*width1-1:0] sub_data_reg [3:0], sub_data_next [3:0];
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| 35 | wire [size*width1-1:0] sub_data_wire;
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| 36 |
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| 37 | integer i;
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| 38 | genvar j;
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| 39 |
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| 40 | generate
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| 41 | for (j = 0; j < size; j = j + 1)
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| 42 | begin : INT_DATA
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| 43 | assign inp_data_wire[0][j*width+width-1:j*width] = inp_data[(3*j+0)*width+width-1:(3*j+0)*width];
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| 44 | assign inp_data_wire[1][j*width+width-1:j*width] = inp_data[(3*j+1)*width+width-1:(3*j+1)*width];
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| 45 | assign inp_data_wire[2][j*width+width-1:j*width] = inp_data[(3*j+2)*width+width-1:(3*j+2)*width];
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| 46 |
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| 47 | lpm_mux #(
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| 48 | .lpm_size(3),
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| 49 | .lpm_type("LPM_MUX"),
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| 50 | .lpm_width(8),
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| 51 | .lpm_widths(2)) mux_unit_1 (
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| 52 | .sel(int_chan_next),
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| 53 | .data({
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| 54 | 2'd2, del_data[(3*j+2)*6+6-1:(3*j+2)*6],
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| 55 | 2'd1, del_data[(3*j+1)*6+6-1:(3*j+1)*6],
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| 56 | 2'd0, del_data[(3*j+0)*6+6-1:(3*j+0)*6]}),
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| 57 | .result(int_addr_wire));
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| 58 |
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| 59 | lpm_add_sub #(
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| 60 | .lpm_direction("SUB"),
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| 61 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 62 | .lpm_representation("UNSIGNED"),
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| 63 | .lpm_type("LPM_ADD_SUB"),
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| 64 | .lpm_width(6)) add_unit_1 (
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| 65 | .dataa(del_addr_reg),
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| 66 | .datab(int_addr_wire[5:0]),
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| 67 | .result(del_addr_wire));
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| 68 |
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| 69 | lpm_add_sub #(
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| 70 | .lpm_direction("SUB"),
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| 71 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 72 | .lpm_representation("SIGNED"),
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| 73 | .lpm_type("LPM_ADD_SUB"),
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| 74 | .lpm_width(width1)) sub_unit_1 (
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| 75 | .dataa({{(width1-width){1'b0}}, inp_data_reg[0][j*width+width-1:j*width]}),
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| 76 | .datab({{(width1-width){1'b0}}, inp_data_wire[3][j*width+width-1:j*width]}),
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| 77 | .result(sub_data_wire[j*width1+width1-1:j*width1]));
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| 78 |
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| 79 | lpm_add_sub #(
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| 80 | .lpm_direction("ADD"),
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| 81 | .lpm_hint("ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"),
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| 82 | .lpm_representation("SIGNED"),
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| 83 | .lpm_type("LPM_ADD_SUB"),
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| 84 | .lpm_width(width1)) acc_unit_1 (
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| 85 | .dataa({sub_data_reg[0][j*width1+width1-1], {(width1-width1){1'b0}}, sub_data_reg[0][j*width1+width1-2:j*width1]}),
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| 86 | .datab(acc_data_reg[0][j*width1+width1-1:j*width1]),
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| 87 | .result(acc_data_wire[j*width1+width1-1:j*width1]));
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| 88 |
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| 89 | end
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| 90 | endgenerate
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| 91 |
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| 92 |
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| 93 | altsyncram #(
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| 94 | .address_aclr_b("NONE"),
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| 95 | .address_reg_b("CLOCK0"),
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| 96 | .clock_enable_input_a("BYPASS"),
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| 97 | .clock_enable_input_b("BYPASS"),
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| 98 | .clock_enable_output_b("BYPASS"),
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| 99 | .intended_device_family("Cyclone III"),
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| 100 | .lpm_type("altsyncram"),
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| 101 | .numwords_a(256),
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| 102 | .numwords_b(256),
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| 103 | .operation_mode("DUAL_PORT"),
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| 104 | .outdata_aclr_b("NONE"),
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| 105 | .outdata_reg_b("CLOCK0"),
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| 106 | .power_up_uninitialized("FALSE"),
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| 107 | .read_during_write_mode_mixed_ports("DONT_CARE"),
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| 108 | .widthad_a(8),
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| 109 | .widthad_b(8),
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| 110 | .width_a(size*width),
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| 111 | .width_b(size*width),
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| 112 | .width_byteena_a(1)) ram_unit_1 (
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| 113 | .wren_a(int_wren_reg),
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| 114 | .clock0(clock),
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| 115 | .address_a(int_addr_reg),
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| 116 | .address_b({int_addr_wire[7:6], del_addr_wire}),
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| 117 | .data_a(inp_data_reg[0]),
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| 118 | .q_b(inp_data_wire[3]),
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| 119 | .aclr0(1'b0),
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| 120 | .aclr1(1'b0),
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| 121 | .addressstall_a(1'b0),
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| 122 | .addressstall_b(1'b0),
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| 123 | .byteena_a(1'b1),
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| 124 | .byteena_b(1'b1),
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| 125 | .clock1(1'b1),
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| 126 | .clocken0(1'b1),
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| 127 | .clocken1(1'b1),
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| 128 | .clocken2(1'b1),
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| 129 | .clocken3(1'b1),
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| 130 | .data_b({(size*width){1'b1}}),
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| 131 | .eccstatus(),
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| 132 | .q_a(),
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| 133 | .rden_a(1'b1),
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| 134 | .rden_b(1'b1),
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| 135 | .wren_b(1'b0));
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| 136 |
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| 137 | always @(posedge clock)
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| 138 | begin
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| 139 | if (reset)
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| 140 | begin
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| 141 | int_wren_reg <= 1'b1;
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| 142 | int_chan_reg <= 2'd0;
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| 143 | int_case_reg <= 3'd0;
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| 144 | del_addr_reg <= 6'd0;
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| 145 | int_addr_reg <= 8'd0;
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| 146 | for(i = 0; i <= 2; i = i + 1)
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| 147 | begin
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| 148 | inp_data_reg[i] <= {(size*width){1'b0}};
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| 149 | out_data_reg[i] <= {(size*width1){1'b0}};
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| 150 | end
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| 151 | for(i = 0; i <= 3; i = i + 1)
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| 152 | begin
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| 153 | sub_data_reg[i] <= {(size*width1){1'b0}};
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| 154 | acc_data_reg[i] <= {(size*width1){1'b0}};
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| 155 | end
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| 156 | end
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| 157 | else
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| 158 | begin
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| 159 | int_wren_reg <= int_wren_next;
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| 160 | int_chan_reg <= int_chan_next;
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| 161 | int_case_reg <= int_case_next;
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| 162 | del_addr_reg <= del_addr_next;
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| 163 | int_addr_reg <= int_addr_next;
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| 164 | for(i = 0; i <= 2; i = i + 1)
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| 165 | begin
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| 166 | inp_data_reg[i] <= inp_data_next[i];
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| 167 | out_data_reg[i] <= out_data_next[i];
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| 168 | end
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| 169 | for(i = 0; i <= 3; i = i + 1)
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| 170 | begin
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| 171 | sub_data_reg[i] <= sub_data_next[i];
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| 172 | acc_data_reg[i] <= acc_data_next[i];
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| 173 | end
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| 174 | end
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| 175 | end
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| 176 |
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| 177 | always @*
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| 178 | begin
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| 179 | int_wren_next = int_wren_reg;
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| 180 | int_chan_next = int_chan_reg;
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| 181 | int_case_next = int_case_reg;
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| 182 | del_addr_next = del_addr_reg;
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| 183 | int_addr_next = int_addr_reg;
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| 184 | for(i = 0; i <= 2; i = i + 1)
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| 185 | begin
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| 186 | inp_data_next[i] = inp_data_reg[i];
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| 187 | out_data_next[i] = out_data_reg[i];
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| 188 | end
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| 189 | for(i = 0; i <= 3; i = i + 1)
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| 190 | begin
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| 191 | sub_data_next[i] = sub_data_reg[i];
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| 192 | acc_data_next[i] = acc_data_reg[i];
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| 193 | end
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| 194 |
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| 195 | case (int_case_reg)
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| 196 | 0:
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| 197 | begin
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| 198 | // write zeros
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| 199 | int_wren_next = 1'b1;
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| 200 | del_addr_next = 6'd0;
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| 201 | int_addr_next = 8'd0;
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| 202 | for(i = 0; i <= 2; i = i + 1)
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| 203 | begin
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| 204 | inp_data_next[i] = {(size*width){1'b0}};
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| 205 | out_data_next[i] = {(size*width1){1'b0}};
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| 206 | end
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| 207 | for(i = 0; i <= 3; i = i + 1)
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| 208 | begin
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| 209 | sub_data_next[i] = {(size*width1){1'b0}};
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| 210 | acc_data_next[i] = {(size*width1){1'b0}};
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| 211 | end
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| 212 |
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| 213 | int_case_next = 3'd1;
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| 214 | end
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| 215 | 1:
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| 216 | begin
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| 217 | // write zeros
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| 218 | int_addr_next = int_addr_reg + 8'd1;
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| 219 | if (&int_addr_reg)
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| 220 | begin
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| 221 | int_wren_next = 1'b0;
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| 222 | int_chan_next = 2'd0;
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| 223 | int_case_next = 3'd2;
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| 224 | end
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| 225 | end
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| 226 | 2: // frame
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| 227 | begin
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| 228 | if (frame)
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| 229 | begin
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| 230 | int_wren_next = 1'b1;
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| 231 |
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| 232 | int_addr_next[7:6] = 2'd0;
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| 233 |
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| 234 | // set read addr for 2nd pipeline
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| 235 | int_chan_next = 2'd1;
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| 236 |
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| 237 | // register input data for 2nd and 3rd sums
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| 238 | inp_data_next[1] = inp_data_wire[1];
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| 239 | inp_data_next[2] = inp_data_wire[2];
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| 240 |
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| 241 | // prepare registers for 1st sum
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| 242 | inp_data_next[0] = inp_data_wire[0];
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| 243 |
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| 244 | sub_data_next[0] = sub_data_reg[1];
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| 245 | acc_data_next[0] = acc_data_reg[1];
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| 246 |
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| 247 | int_case_next = 3'd3;
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| 248 | end
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| 249 |
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| 250 | end
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| 251 | 3: // 1st sum
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| 252 | begin
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| 253 | int_addr_next[7:6] = 2'd1;
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| 254 |
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| 255 | // set read addr for 3rd pipeline
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| 256 | int_chan_next = 2'd2;
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| 257 |
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| 258 | // prepare registers for 2nd sum
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| 259 | inp_data_next[0] = inp_data_reg[1];
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| 260 |
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| 261 | sub_data_next[0] = sub_data_reg[2];
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| 262 | acc_data_next[0] = acc_data_reg[2];
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| 263 |
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| 264 | // register 1st sum
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| 265 | sub_data_next[1] = sub_data_wire;
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| 266 | acc_data_next[1] = acc_data_wire;
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| 267 | out_data_next[0] = acc_data_wire;
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| 268 |
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| 269 | int_case_next = 3'd4;
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| 270 | end
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| 271 | 4: // 2nd sum
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| 272 | begin
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| 273 | int_addr_next[7:6] = 2'd2;
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| 274 |
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| 275 | // prepare registers for 3rd sum
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| 276 | inp_data_next[0] = inp_data_reg[2];
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| 277 |
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| 278 | sub_data_next[0] = sub_data_reg[3];
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| 279 | acc_data_next[0] = acc_data_reg[3];
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| 280 |
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| 281 | // register 2nd sum
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| 282 | sub_data_next[2] = sub_data_wire;
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| 283 | acc_data_next[2] = acc_data_wire;
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| 284 | out_data_next[1] = acc_data_wire;
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| 285 |
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| 286 | del_addr_next = del_addr_reg + 6'd1;
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| 287 |
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| 288 | int_case_next = 3'd5;
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| 289 | end
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| 290 | 5: // 3rd sum
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| 291 | begin
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| 292 | int_wren_next = 1'b0;
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| 293 |
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| 294 | // set read addr for 1st pipeline
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| 295 | int_chan_next = 2'd0;
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| 296 |
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| 297 | // register 3rd sum
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| 298 | sub_data_next[3] = sub_data_wire;
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| 299 | acc_data_next[3] = acc_data_wire;
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| 300 | out_data_next[2] = acc_data_wire;
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| 301 |
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| 302 | int_addr_next[5:0] = del_addr_reg;
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| 303 |
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| 304 | int_case_next = 3'd2;
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| 305 | end
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| 306 | default:
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| 307 | begin
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| 308 | int_case_next = 3'd0;
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| 309 | end
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| 310 | endcase
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| 311 | end
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| 312 |
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| 313 | assign out_data = {out_data_reg[2], out_data_reg[1], out_data_reg[0]};
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| 314 |
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| 315 | endmodule
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