source: sandbox/MultiChannelUSB/amplitude.v@ 156

Last change on this file since 156 was 155, checked in by demin, 13 years ago

add one delay register

File size: 2.4 KB
Line 
1module amplitude
2 #(
3 parameter width = 12 // bit width of the input data
4 )
5 (
6 input wire clock, frame, reset,
7 input wire [width-1:0] cfg_data,
8 input wire [width-1:0] inp_data,
9 output wire [width-1:0] out_data,
10 output wire out_flag
11 );
12
13 reg int_case_reg, int_case_next;
14 reg out_flag_reg, out_flag_next;
15 reg int_flag_reg, int_flag_next;
16 reg [width-1:0] int_mini_reg, int_mini_next;
17 reg [width-1:0] out_data_reg, out_data_next;
18 reg [width-1:0] inp_data_reg [1:0], inp_data_next [1:0];
19
20 wire int_comp_wire;
21 reg int_comp_reg, int_comp_next;
22
23 assign int_comp_wire = (inp_data_reg[1] < inp_data);
24
25 always @(posedge clock)
26 begin
27 if (reset)
28 begin
29 int_case_reg <= 1'b0;
30 int_mini_reg <= {(width){1'b0}};
31 inp_data_reg[0] <= {(width){1'b0}};
32 inp_data_reg[1] <= {(width){1'b0}};
33 out_data_reg <= {(width){1'b0}};
34 out_flag_reg <= 1'b0;
35 int_flag_reg <= 1'b0;
36 int_comp_reg <= 1'b0;
37 end
38 else
39 begin
40 int_case_reg <= int_case_next;
41 int_mini_reg <= int_mini_next;
42 inp_data_reg[0] <= inp_data_next[0];
43 inp_data_reg[1] <= inp_data_next[1];
44 out_data_reg <= out_data_next;
45 out_flag_reg <= out_flag_next;
46 int_flag_reg <= int_flag_next;
47 int_comp_reg <= int_comp_next;
48 end
49 end
50
51 always @*
52 begin
53 int_case_next = int_case_reg;
54 int_mini_next = int_mini_reg;
55 inp_data_next[0] = inp_data_reg[0];
56 inp_data_next[1] = inp_data_reg[1];
57 out_data_next = out_data_reg;
58 out_flag_next = out_flag_reg;
59 int_flag_next = int_flag_reg;
60 int_comp_next = int_comp_reg;
61
62 case (int_case_reg)
63 0:
64 begin
65 if (frame)
66 begin
67 inp_data_next[0] = inp_data;
68 inp_data_next[1] = inp_data_reg[0];
69 int_comp_next = int_comp_wire;
70 out_data_next = {(width){1'b0}};
71 out_flag_next = 1'b0;
72 // minimum
73 if ((~int_comp_reg) & (int_comp_wire))
74 begin
75 int_mini_next = inp_data_reg[0];
76 int_flag_next = 1'b1;
77 end
78 // maximum
79 else if ((int_comp_reg) & (~int_comp_wire) & (int_flag_reg))
80 begin
81 out_data_next = inp_data_reg[0] - int_mini_reg;
82 int_flag_next = 1'b0;
83 int_case_next = 1'b1;
84 end
85 end
86 end
87
88 1:
89 begin
90 out_flag_next = (out_data_reg >= cfg_data);
91 int_case_next = 1'b0;
92 end
93
94 endcase
95 end
96
97 assign out_data = out_data_reg;
98 assign out_flag = out_flag_reg;
99
100endmodule
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