source: sandbox/MultiChannelUSB/adc_lvds.v@ 109

Last change on this file since 109 was 107, checked in by demin, 14 years ago

Starting to test signal shaping algorithms

File size: 2.2 KB
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1module adc_lvds
2 #(
3 parameter size = 3, // number of channels
4 parameter width = 12 // channel resolution
5 )
6 (
7 input wire clock,
8
9 input wire lvds_dco,
10 input wire lvds_fco,
11 input wire [size-1:0] lvds_d,
12
13 input wire [11:0] test,
14 input wire [11:0] trig,
15
16 output wire adc_frame,
17 output wire [size*width-1+12:0] adc_data
18
19 );
20
21 reg state, int_rdreq, adc_frame_reg;
22 wire int_wrfull, int_rdempty;
23
24 reg [size-1:0] int_data_h, int_data_l;
25
26 reg [size*width-1:0] int_data_reg;
27 wire [size*width-1:0] int_data_wire;
28
29 wire [size*width-1+12:0] int_q_wire;
30 reg [size*width-1+12:0] adc_data_reg;
31
32
33 genvar j;
34
35 generate
36 for (j = 0; j < size-1; j = j + 1)
37 begin : INT_DATA
38 assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_h[j], int_data_l[j]};
39// assign int_data_wire[j*width+width-1:j*width] = test;
40 end
41 endgenerate
42 assign int_data_wire[(size-1)*width+width-1:(size-1)*width] = test;
43
44 dcfifo #(
45 .intended_device_family("Cyclone III"),
46 .lpm_numwords(16),
47 .lpm_showahead("ON"),
48 .lpm_type("dcfifo"),
49 .lpm_width(size*width+12),
50 .lpm_widthu(4),
51 .rdsync_delaypipe(4),
52 .wrsync_delaypipe(4),
53 .overflow_checking("ON"),
54 .underflow_checking("ON"),
55 .use_eab("ON")) fifo_unit (
56 .data({trig, int_data_wire}),
57 .rdclk(clock),
58 .rdreq((~int_rdempty) & int_rdreq),
59 .wrclk(lvds_fco),
60 .wrreq(~int_wrfull),
61 .q(int_q_wire),
62 .rdempty(int_rdempty),
63 .wrfull(int_wrfull),
64 .aclr(),
65 .rdfull(),
66 .rdusedw(),
67 .wrempty(),
68 .wrusedw());
69
70 always @ (posedge clock)
71 begin
72 case (state)
73 1'b0:
74 begin
75 int_rdreq <= 1'b1;
76 adc_frame_reg <= 1'b0;
77 state <= 1'b1;
78 end
79
80 1'b1:
81 begin
82 if (~int_rdempty)
83 begin
84 int_rdreq <= 1'b0;
85 adc_frame_reg <= 1'b1;
86 adc_data_reg <= int_q_wire;
87 state <= 1'b0;
88 end
89 end
90 endcase
91 end
92
93 always @ (negedge lvds_dco)
94 begin
95 int_data_l <= lvds_d;
96 end
97
98 always @ (posedge lvds_dco)
99 begin
100 int_data_h <= lvds_d;
101 int_data_reg <= int_data_wire;
102 end
103
104 assign adc_frame = adc_frame_reg;
105 assign adc_data = adc_data_reg;
106
107endmodule
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