source: sandbox/MultiChannelUSB/Paella.v@ 128

Last change on this file since 128 was 126, checked in by demin, 14 years ago

simplified 900ns version

File size: 10.6 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire I2C_SDA,
8 inout wire I2C_SCL,
9 inout wire [4:0] CON_A,
10 input wire [15:0] CON_B,
11 input wire [12:0] CON_C,
12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
17 input wire [2:0] ADC_D,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 localparam N = 3;
46
47 // Turn output ports off
48/*
49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
53*/
54 assign RAM_CLK = sys_clock;
55 assign RAM_CE1 = 1'b0;
56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
59 assign CON_A = 5'bz;
60 assign USB_PA0 = 1'bz;
61 assign USB_PA1 = 1'bz;
62 assign USB_PA3 = 1'bz;
63 assign USB_PA7 = 1'bz;
64// assign RAM_DQAP = 1'bz;
65// assign RAM_DQA = 8'bz;
66// assign RAM_DQBP = 1'bz;
67// assign RAM_DQB = 8'bz;
68
69 assign USB_PA2 = ~usb_rden;
70 assign USB_PA4 = usb_addr[0];
71 assign USB_PA5 = usb_addr[1];
72 assign USB_PA6 = ~usb_pktend;
73
74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
75 wire usb_tx_wrreq, usb_rx_rdreq;
76 wire usb_tx_full, usb_rx_empty;
77 wire [7:0] usb_tx_data, usb_rx_data;
78 wire [1:0] usb_addr;
79
80 assign USB_SLRD = ~usb_rdreq;
81 assign USB_SLWR = ~usb_wrreq;
82
83 usb_fifo usb_unit
84 (
85 .usb_clock(USB_IFCLK),
86 .usb_data(USB_PB),
87 .usb_full(~USB_FLAGB),
88 .usb_empty(~USB_FLAGA),
89 .usb_wrreq(usb_wrreq),
90 .usb_rdreq(usb_rdreq),
91 .usb_rden(usb_rden),
92 .usb_pktend(usb_pktend),
93 .usb_addr(usb_addr),
94
95 .clock(sys_clock),
96
97 .tx_full(usb_tx_full),
98 .tx_wrreq(usb_tx_wrreq),
99 .tx_data(usb_tx_data),
100
101 .rx_empty(usb_rx_empty),
102 .rx_rdreq(usb_rx_rdreq),
103 .rx_q(usb_rx_data)
104 );
105
106 wire [11:0] osc_mux_data [4:0];
107
108 wire [11:0] trg_mux_data;
109 wire trg_flag;
110
111 wire [2:0] coi_data;
112 wire coi_flag;
113
114 wire [7*12-1:0] int_mux_data [N-1:0];
115
116 wire ana_dead [N-1:0];
117 wire ana_good [N-1:0];
118 wire [11:0] ana_data [N-1:0];
119 wire [11:0] ana_base [N-1:0];
120
121 wire amp_flag [N-1:0];
122 wire [11:0] amp_data [N-1:0];
123
124 wire cnt_good [N-1:0];
125 wire [15:0] cnt_bits_wire;
126
127 wire sys_clock, sys_frame;
128
129 wire [11:0] adc_data [N-1:0];
130 wire [11:0] sys_data [N-1:0];
131 wire [11:0] tst_data;
132
133 wire [11:0] cmp_data;
134 wire [11:0] del_data;
135
136 wire [15:0] uwt_data1 [N-1:0];
137 wire [18:0] uwt_data2 [N-1:0];
138 wire [1:0] uwt_flag1 [N-1:0];
139 wire [1:0] uwt_flag2 [N-1:0];
140
141 wire [24:0] cic_data1 [N-1:0];
142 wire [24:0] cic_data2 [N-1:0];
143 wire [24:0] cic_data3 [N-1:0];
144
145 wire [11:0] dec_data [N-1:0];
146
147 wire [1:0] ext_flag [N-1:0];
148
149 wire i2c_reset;
150
151 sys_pll sys_pll_unit(
152 .inclk0(CLK_50MHz),
153 .c0(sys_clock));
154
155 test test_unit(
156 .clock(ADC_FCO),
157 .data(tst_data));
158
159 adc_lvds #(
160 .size(3),
161 .width(12)) adc_lvds_unit (
162 .clock(sys_clock),
163 .lvds_dco(ADC_DCO),
164 .lvds_fco(ADC_FCO),
165 .lvds_d(ADC_D),
166 .test(tst_data),
167 .trig({CON_B[9:0], TRG[1:0]}),
168 .adc_frame(sys_frame),
169 .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
170
171 wire [15:0] cfg_bits [31:0];
172 wire [511:0] int_cfg_bits;
173
174 wire [39:0] cfg_mux_selector;
175
176 wire cfg_reset;
177
178 wire [11:0] bus_ssel;
179 wire bus_wren;
180 wire [31:0] bus_addr;
181 wire [15:0] bus_mosi;
182 wire [15:0] bus_miso [10:0];
183 wire [11:0] bus_busy;
184
185 wire [15:0] mrg_bus_miso;
186 wire mrg_bus_busy;
187
188 wire [11*16-1:0] int_bus_miso;
189
190 genvar j;
191
192 generate
193 for (j = 0; j < 32; j = j + 1)
194 begin : CONFIGURATION_OUTPUT
195 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
196 end
197 endgenerate
198
199 configuration configuration_unit (
200 .clock(sys_clock),
201 .reset(cfg_reset),
202 .bus_ssel(bus_ssel[0]),
203 .bus_wren(bus_wren),
204 .bus_addr(bus_addr[4:0]),
205 .bus_mosi(bus_mosi),
206 .bus_miso(bus_miso[0]),
207 .bus_busy(bus_busy[0]),
208 .cfg_bits(int_cfg_bits));
209
210 generate
211 for (j = 0; j < 3; j = j + 1)
212 begin : MUX_DATA
213 assign int_mux_data[j] = {
214// {4'd0, amp_flag[j], 7'd0},
215// dec_data[j][37:26],
216// dec_data[j][36:25],
217// dec_data[j][35:24],
218 dec_data[j][11:0],
219 dec_data[j][11:0],
220 amp_data[j][11:0],
221 {ext_flag[j][1], 11'd0},
222 {ext_flag[j][0], 11'd0},
223 cic_data3[j][23:12],
224 sys_data[j]};
225 end
226 endgenerate
227
228 assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
229
230 lpm_mux #(
231 .lpm_size(7*3),
232 .lpm_type("LPM_MUX"),
233 .lpm_width(12),
234 .lpm_widths(5)) trg_mux_unit (
235 .sel(cfg_bits[4][12:8]),
236 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
237 .result(trg_mux_data));
238
239 generate
240 for (j = 0; j < 5; j = j + 1)
241 begin : OSC_CHAIN
242
243 lpm_mux #(
244 .lpm_size(7*3),
245 .lpm_type("LPM_MUX"),
246 .lpm_width(12),
247 .lpm_widths(5)) osc_mux_unit (
248 .sel(cfg_mux_selector[j*8+4:j*8]),
249 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
250 .result(osc_mux_data[j]));
251 end
252 endgenerate
253
254 trigger trigger_unit (
255 .clock(sys_clock),
256 .frame(sys_frame),
257 .reset(cfg_bits[0][0]),
258 .cfg_data(cfg_bits[5][11:0]),
259 .trg_data(trg_mux_data),
260 .trg_flag(trg_flag));
261
262 oscilloscope oscilloscope_unit (
263 .clock(sys_clock),
264 .frame(sys_frame),
265 .reset(cfg_bits[0][1]),
266 .cfg_data(cfg_bits[5][12]),
267 .trg_flag(trg_flag),
268 .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
269 .ram_wren(RAM_WE),
270 .ram_addr(RAM_ADDR),
271 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
272 .bus_ssel(bus_ssel[1]),
273 .bus_wren(bus_wren),
274 .bus_addr(bus_addr[19:0]),
275 .bus_mosi(bus_mosi),
276 .bus_miso(bus_miso[1]),
277 .bus_busy(bus_busy[1]));
278
279 filter #(.size(3), .width(12)) filter_unit (
280 .clock(sys_clock),
281 .frame(sys_frame),
282 .reset(1'b0),
283 .inp_data({sys_data[2], sys_data[1], sys_data[0]}),
284 .out_data2({cic_data2[2], cic_data2[1], cic_data2[0]}),
285 .out_data3({cic_data3[2], cic_data3[1], cic_data3[0]}),
286 .out_data({cic_data1[2], cic_data1[1], cic_data1[0]}));
287
288 deconv #(.size(1), .shift(25), .width(24), .widthr(12)) deconv_unit (
289 .clock(sys_clock),
290 .frame(sys_frame),
291 .reset(1'b0),
292 .del_data({6'd18, 6'd18, 6'd18}),
293 .amp_data({4'd9, 4'd9, 4'd9}),
294 .tau_data({16'd8820, 16'd8820, 16'd8820}),
295// .del_data({cfg_bits[16][5:0], cfg_bits[15][13:8], cfg_bits[15][5:0]}),
296// .amp_data({cfg_bits[18][7:0], cfg_bits[17][15:8], cfg_bits[17][7:0]}),
297// .tau_data({cfg_bits[21], cfg_bits[20], cfg_bits[19]}),
298 .inp_data({cic_data3[2][23:0], cic_data3[1][23:0], cic_data3[0][23:0]}),
299 .out_data({dec_data[2], dec_data[1], dec_data[0]}));
300
301
302 generate
303 for (j = 0; j < 3; j = j + 1)
304 begin : MCA_CHAIN
305
306 assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
307/*
308 uwt_bior31 #(.level(1), .width(13)) uwt_1_unit (
309 .clock(sys_clock),
310 .frame(sys_frame),
311 .reset(1'b0),
312 .inp_data(dec_data[j][12:0]),
313 .out_data(uwt_data1[j]),
314 .out_flag(uwt_flag1[j]));
315
316 uwt_bior31 #(.level(1), .width(16)) uwt_2_unit (
317 .clock(sys_clock),
318 .frame(sys_frame),
319 .reset(1'b0),
320 .inp_data(uwt_data1[j]),
321 .out_data(uwt_data2[j]),
322 .out_flag(uwt_flag2[j]));
323*/
324 extrema #(.width(12)) extrema_unit (
325 .clock(sys_clock),
326 .frame(sys_frame),
327 .reset(1'b0),
328// .inp_data(cic_data3[j][26:15]),
329 .inp_data(dec_data[j]),
330 .out_flag(ext_flag[j]));
331
332 analyser analyser_unit (
333 .clock(sys_clock),
334 .frame(sys_frame),
335 .reset(cfg_bits[0][2+j]),
336 .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
337 .uwt_flag(uwt_flag2[j]),
338 .uwt_data(uwt_data2[j][18:7]),
339 .ana_dead(ana_dead[j]),
340 .ana_good(ana_good[j]),
341 .ana_data(ana_data[j]),
342 .ana_base(ana_base[j]));
343
344 amplitude #(.width(12)) amplitude_unit (
345 .clock(sys_clock),
346 .frame(sys_frame),
347 .reset(cfg_bits[0][2+j]),
348// .cfg_data(cfg_bits[12][11:0]),
349 .cfg_data(12'd5),
350// .inp_data(cic_data3[j][22:11]),
351 .inp_data(dec_data[j]),
352 .out_flag(amp_flag[j]),
353 .out_data(amp_data[j]));
354 end
355 endgenerate
356
357 histogram32 histogram32_unit (
358 .clock(sys_clock),
359 .frame(sys_frame),
360 .reset(cfg_bits[0][5]),
361 .hst_good((ana_good[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
362 .hst_data(ana_data[0]),
363/*
364 .hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
365 .hst_data(amp_data[j]),
366*/
367 .bus_ssel(bus_ssel[2]),
368 .bus_wren(bus_wren),
369 .bus_addr(bus_addr[12:0]),
370 .bus_mosi(bus_mosi),
371 .bus_miso(bus_miso[2]),
372 .bus_busy(bus_busy[2]));
373
374 counter hst_counter_unit (
375 .clock(sys_clock),
376 .frame((sys_frame) & (~ana_dead[0])),
377// .frame(sys_frame),
378 .reset(cfg_bits[0][8]),
379 .setup(cfg_bits[13][0]),
380 .count(cfg_bits[13][1]),
381 .bus_ssel(bus_ssel[5]),
382 .bus_wren(bus_wren),
383 .bus_addr(bus_addr[1:0]),
384 .bus_mosi(bus_mosi),
385 .bus_miso(bus_miso[5]),
386 .bus_busy(bus_busy[5]),
387 .cnt_good(cnt_good[0]));
388
389
390 i2c_fifo i2c_unit(
391 .clock(sys_clock),
392 .reset(i2c_reset),
393/*
394 normal connection
395 .i2c_sda(I2C_SDA),
396 .i2c_scl(I2C_SCL),
397
398 following is a cross wire connection for EPT
399*/
400 .i2c_sda(I2C_SCL),
401 .i2c_scl(I2C_SDA),
402
403 .bus_ssel(bus_ssel[11]),
404 .bus_wren(bus_wren),
405 .bus_mosi(bus_mosi),
406 .bus_busy(bus_busy[11]));
407
408 generate
409 for (j = 0; j < 11; j = j + 1)
410 begin : BUS_OUTPUT
411 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
412 end
413 endgenerate
414
415 lpm_mux #(
416 .lpm_size(11),
417 .lpm_type("LPM_MUX"),
418 .lpm_width(16),
419 .lpm_widths(4)) bus_miso_mux_unit (
420 .sel(bus_addr[31:28]),
421 .data(int_bus_miso),
422 .result(mrg_bus_miso));
423
424 lpm_mux #(
425 .lpm_size(12),
426 .lpm_type("LPM_MUX"),
427 .lpm_width(1),
428 .lpm_widths(4)) bus_busy_mux_unit (
429 .sel(bus_addr[31:28]),
430 .data(bus_busy),
431 .result(mrg_bus_busy));
432
433 lpm_decode #(
434 .lpm_decodes(12),
435 .lpm_type("LPM_DECODE"),
436 .lpm_width(4)) lpm_decode_unit (
437 .data(bus_addr[31:28]),
438 .eq(bus_ssel));
439
440
441 control control_unit (
442 .clock(sys_clock),
443 .rx_empty(usb_rx_empty),
444 .tx_full(usb_tx_full),
445 .rx_data(usb_rx_data),
446 .rx_rdreq(usb_rx_rdreq),
447 .tx_wrreq(usb_tx_wrreq),
448 .tx_data(usb_tx_data),
449 .bus_wren(bus_wren),
450 .bus_addr(bus_addr),
451 .bus_mosi(bus_mosi),
452 .bus_miso(mrg_bus_miso),
453 .bus_busy(mrg_bus_busy),
454 .led(LED));
455
456/*
457 altserial_flash_loader #(
458 .enable_shared_access("OFF"),
459 .enhanced_mode(1),
460 .intended_device_family("Cyclone III")) sfl_unit (
461 .noe(1'b0),
462 .asmi_access_granted(),
463 .asmi_access_request(),
464 .data0out(),
465 .dclkin(),
466 .scein(),
467 .sdoin());
468*/
469
470endmodule
Note: See TracBrowser for help on using the repository browser.