module Paella
	(
		input	wire			CLK_100MHz,
		output	wire			LED,

		input	wire			ADC_DCO,
		input	wire			ADC_FCO,
		input	wire	[5:0]	ADC_D,

		output	wire	[1:0]	SPI_SEL,
		output	wire			SPI_SDO,
		output	wire			SPI_CLK,
		output	wire			ADC_RST,

		output	wire			USB_SLRD,
		output	wire			USB_SLWR,
		input	wire			USB_IFCLK,
		input	wire			USB_FLAGA, // EMPTY flag for EP6
		input	wire			USB_FLAGB, // FULL flag for EP8
		output	wire			USB_PA2,
		output	wire			USB_PA4,
		output	wire			USB_PA6,
		inout	wire	[7:0]	USB_PB,

		output	wire			RAM_CLK,
		output	wire			RAM_WE,
		output	wire	[21:0]	RAM_ADDR,
		inout	wire			RAM_DQAP,
		inout	wire	[7:0]	RAM_DQA,
		inout	wire			RAM_DQBP,
		inout	wire	[7:0]	RAM_DQB
	);

	localparam	N		=	12;

	//	Turn output ports off
/*
	assign	RAM_CLK		=	1'b0;
	assign	RAM_CE1		=	1'b0;
	assign	RAM_WE		=	1'b0;
	assign	RAM_ADDR	=	20'h00000;
*/
	assign	ADC_RST = 1'b0;

	assign	RAM_CLK = sys_clock;

	assign	USB_PA2		=	~usb_rden;
	assign	USB_PA4		=	usb_addr;
	assign	USB_PA6		=	~usb_pktend;

	wire			usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
	wire			usb_tx_wrreq, usb_rx_rdreq;
	wire			usb_tx_full, usb_rx_empty;
	wire	[7:0]	usb_tx_data, usb_rx_data;
	wire			usb_addr;

	assign	USB_SLRD = ~usb_rdreq;
	assign	USB_SLWR = ~usb_wrreq;

	usb_fifo usb_unit
	(
		.usb_clock(USB_IFCLK),
		.usb_data(USB_PB),
		.usb_full(~USB_FLAGB),
		.usb_empty(~USB_FLAGA),
		.usb_wrreq(usb_wrreq),
		.usb_rdreq(usb_rdreq),
		.usb_rden(usb_rden),
		.usb_pktend(usb_pktend),
		.usb_addr(usb_addr),

		.clock(sys_clock),

		.tx_full(usb_tx_full),
		.tx_wrreq(usb_tx_wrreq),
		.tx_data(usb_tx_data),

		.rx_empty(usb_rx_empty),
		.rx_rdreq(usb_rx_rdreq),
		.rx_q(usb_rx_data)
	);
		
	wire	[11:0]	osc_mux_data [4:0];

	wire	[11:0]	trg_mux_data;
	wire			trg_flag;

	wire	[2:0]	coi_data;
	wire			coi_flag;

	wire	[4*12-1:0]	int_mux_data [N-1:0];

	wire			amp_flag1 [N-1:0];
	wire	[11:0]	amp_data1 [N-1:0];

	wire			amp_flag2 [N-1:0];
	wire	[11:0]	amp_data2 [N-1:0];

	wire			cnt_good [N-1:0];
	wire	[15:0]	cnt_bits_wire;

	wire			sys_clock, sys_frame;

    wire	[11:0]	adc_data [N-1:0];
    wire	[11:0]	sys_data [N-1:0];
	wire	[11:0]	tst_data;

    wire	[11:0]	cmp_data;
    wire	[11:0]	del_data;

	wire	[20:0]	cic_data [N-1:0];

	wire	[11:0]	dec_data [N-1:0];
	wire	[11:0]	clp_data [N-1:0];
	wire	[11:0]	tmp_data [1:0];

	wire			i2c_reset;
/*
	sys_pll sys_pll_unit(
		.inclk0(CLK_100MHz),
		.c0(sys_clock),
		.c1(ADC_DCO),
		.c2(ADC_FCO));

	wire			ADC_DCO, ADC_FCO;

	test test_unit(
		.clock(ADC_FCO),
		.data(tst_data));

	adc_lvds #(
		.size(3),
		.width(12)) adc_lvds_unit (
		.clock(sys_clock),
		.lvds_dco(ADC_DCO),
		.lvds_fco(ADC_FCO),
		.lvds_d(36'd0),
		.test(tst_data),
		.trig(12'd0),
		.adc_frame(sys_frame),
		.adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
*/
	sys_pll sys_pll_unit(
		.inclk0(CLK_100MHz),
		.c0(sys_clock));

	adc_lvds #(
		.size(6),
		.width(24)) adc_lvds_unit (
		.clock(sys_clock),
		.lvds_dco(ADC_DCO),
		.lvds_fco(ADC_FCO),
		.lvds_d({ADC_D[5], ADC_D[4], ADC_D[3], ADC_D[2], ADC_D[1], ADC_D[0]}),
		.adc_frame(sys_frame),
		.adc_data({
			adc_data[11], adc_data[10], adc_data[9], adc_data[8],
			adc_data[7], adc_data[6], adc_data[5], adc_data[4],
			adc_data[3], adc_data[2], adc_data[1], adc_data[0]}));

	wire	[15:0]	cfg_bits [31:0];
	wire	[511:0]	int_cfg_bits;

	wire	[39:0]	cfg_mux_selector;

	wire 			cfg_reset;

	wire 	[12:0]	bus_ssel;
	wire			bus_wren;
	wire	[31:0]	bus_addr;
	wire	[15:0]	bus_mosi;
	wire 	[15:0]	bus_miso [10:0];
	wire 	[12:0]	bus_busy;

	wire 	[15:0]	mrg_bus_miso;
	wire 			mrg_bus_busy;

	wire 	[12*16-1:0]	int_bus_miso;

	genvar j;

	generate
		for (j = 0; j < 32; j = j + 1)
		begin : CONFIGURATION_OUTPUT
			assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
		end
	endgenerate

	configuration configuration_unit (
		.clock(sys_clock),
		.reset(cfg_reset),
		.bus_ssel(bus_ssel[0]),
		.bus_wren(bus_wren),
		.bus_addr(bus_addr[4:0]),
		.bus_mosi(bus_mosi),
		.bus_miso(bus_miso[0]),
		.bus_busy(bus_busy[0]),
		.cfg_bits(int_cfg_bits));

	generate
		for (j = 0; j < 12; j = j + 1)
		begin : MUX_DATA
			assign int_mux_data[j] = {
				clp_data[j][11:0],
				dec_data[j][11:0],
				cic_data[j][19:8],
				sys_data[j]};
		end
	endgenerate

	assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};

	lpm_mux #(
		.lpm_size(4*12),
		.lpm_type("LPM_MUX"),
		.lpm_width(12),
		.lpm_widths(6)) trg_mux_unit (
		.sel(cfg_bits[4][13:8]),
		.data({
			int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
			int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
			int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
		.result(trg_mux_data));

	generate
		for (j = 0; j < 5; j = j + 1)
		begin : OSC_CHAIN
		
			lpm_mux #(
				.lpm_size(4*12),
				.lpm_type("LPM_MUX"),
				.lpm_width(12),
				.lpm_widths(6)) osc_mux_unit (
				.sel(cfg_mux_selector[j*8+5:j*8]),
				.data({
					int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
					int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
					int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
				.result(osc_mux_data[j]));
		end
	endgenerate

	trigger trigger_unit (
		.clock(sys_clock),
		.frame(sys_frame),
		.reset(cfg_bits[0][0]),
		.cfg_data(cfg_bits[5][11:0]),
		.trg_data(trg_mux_data),
		.trg_flag(trg_flag));
	
	oscilloscope oscilloscope_unit (
		.clock(sys_clock),
		.frame(sys_frame),
		.reset(cfg_bits[0][1]),
		.cfg_data(cfg_bits[5][12]),
		.trg_flag(trg_flag),
		.osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
		.ram_wren(RAM_WE),
		.ram_addr(RAM_ADDR),
		.ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
		.bus_ssel(bus_ssel[1]),
		.bus_wren(bus_wren),
		.bus_addr(bus_addr[19:0]),
		.bus_mosi(bus_mosi),
		.bus_miso(bus_miso[1]),
		.bus_busy(bus_busy[1]));

	new_filter #(.size(12), .width(12)) filter_unit (
		.clock(sys_clock),
		.frame(sys_frame),
		.reset(1'b0),
		.inp_data({
			sys_data[11], sys_data[10], sys_data[9], sys_data[08],
			sys_data[7], sys_data[6], sys_data[5], sys_data[4],
			sys_data[3], sys_data[2], sys_data[1], sys_data[0]}),
		.out_data({
			cic_data[11], cic_data[10], cic_data[9], cic_data[8],
			cic_data[7], cic_data[6], cic_data[5], cic_data[4],
			cic_data[3], cic_data[2], cic_data[1], cic_data[0]}));

	generate
		for (j = 0; j < 3; j = j + 1)
		begin : DECONV_CHAIN
	
			deconv #(.shift(22), .width(20), .widthr(12)) deconv_unit (
				.clock(sys_clock),
				.frame(sys_frame),
				.reset(1'b0),
				.del_data({6'd14, 6'd14, 6'd14, 6'd14}),
				.amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
				.tau_data({16'd16320, 16'd16320, 16'd16320, 16'd16320}),
//				.del_data({cfg_bits[16][5:0], cfg_bits[15][13:8], cfg_bits[15][5:0]}),
//				.amp_data({cfg_bits[18][7:0], cfg_bits[17][15:8], cfg_bits[17][7:0]}),
//				.tau_data({cfg_bits[21], cfg_bits[20], cfg_bits[19]}),
				.inp_data({
					cic_data[j*4+3][19:0], cic_data[j*4+2][19:0],
					cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}),
				.out_data({
					dec_data[j*4+3], dec_data[j*4+2],
					dec_data[j*4+1], dec_data[j*4+0]}));
		
		
			clip #(.shift(22), .width(20), .widthr(12)) clip_unit (
				.clock(sys_clock),
				.frame(sys_frame),
				.reset(1'b0),
				.del_data({6'd14, 6'd14, 6'd14, 6'd14}),
				.amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
				.tau_data({16'd17166, 16'd17166, 16'd17166, 16'd17166}),
				.inp_data({
					cic_data[j*4+3][19:0], cic_data[j*4+2][19:0],
					cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}),
				.out_data({
					clp_data[j*4+3], clp_data[j*4+2], 
					clp_data[j*4+1], clp_data[j*4+0]}));
		end
	endgenerate

	generate
		for (j = 0; j < 12; j = j + 1)
		begin : MCA_CHAIN

			assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);

			amplitude #(.width(12)) amplitude_unit_1 (
				.clock(sys_clock),
				.frame(sys_frame),
				.reset(cfg_bits[0][2+j]),
				.cfg_data({1'b0, 12'd0, 12'd5}),
//				.cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
				.inp_data(dec_data[j]),
				.out_flag(amp_flag1[j]),
				.out_data(amp_data1[j]));

			amplitude #(.width(12)) amplitude_unit_2 (
				.clock(sys_clock),
				.frame(sys_frame),
				.reset(cfg_bits[0][2+j]),
				.cfg_data({1'b0, 12'd0, 12'd5}),
//				.cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
//				.inp_data(dec_data[j]),
				.inp_data(clp_data[j]),
				.out_flag(amp_flag2[j]),
				.out_data(amp_data2[j]));
		end
	endgenerate

	histogram32 histogram32_unit (
		.clock(sys_clock),
		.frame(sys_frame),
		.reset(cfg_bits[0][5]),
		.hst_good((amp_flag1[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
		.hst_data(amp_data1[0]),
/*
		.hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
		.hst_data(amp_data[j]),
*/
		.bus_ssel(bus_ssel[2]),
		.bus_wren(bus_wren),
		.bus_addr(bus_addr[12:0]),
		.bus_mosi(bus_mosi),
		.bus_miso(bus_miso[2]),
		.bus_busy(bus_busy[2]));

	counter hst_counter_unit (
		.clock(sys_clock),
//		.frame((sys_frame) & (~ana_dead[0])),
		.frame(sys_frame),
		.reset(cfg_bits[0][8]),
		.setup(cfg_bits[13][0]),
		.count(cfg_bits[13][1]),
		.bus_ssel(bus_ssel[5]),
		.bus_wren(bus_wren),
		.bus_addr(bus_addr[1:0]),
		.bus_mosi(bus_mosi),
		.bus_miso(bus_miso[5]),
		.bus_busy(bus_busy[5]),
		.cnt_good(cnt_good[0]));


	i2c_fifo i2c_unit(
		.clock(sys_clock),
		.reset(i2c_reset),
/*
		normal connection
		.i2c_sda(I2C_SDA),
		.i2c_scl(I2C_SCL),

		following is a cross wire connection for EPT
*/
		.i2c_sda(I2C_SCL),
		.i2c_scl(I2C_SDA),
		
		.bus_ssel(bus_ssel[11]),
		.bus_wren(bus_wren),
		.bus_mosi(bus_mosi),
		.bus_busy(bus_busy[11]));

	spi_fifo spi_unit(
		.clock(sys_clock),
		.reset(1'b0),
		.spi_sel(SPI_SEL),
		.spi_sdo(SPI_SDO),
		.spi_clk(SPI_CLK),
		
		.bus_ssel(bus_ssel[12]),
		.bus_wren(bus_wren),
		.bus_mosi(bus_mosi),
		.bus_busy(bus_busy[12]));

	generate
		for (j = 0; j < 11; j = j + 1)
		begin : BUS_OUTPUT
			assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
		end
	endgenerate

	lpm_mux #(
		.lpm_size(12),
		.lpm_type("LPM_MUX"),
		.lpm_width(16),
		.lpm_widths(4)) bus_miso_mux_unit (
		.sel(bus_addr[31:28]),
		.data(int_bus_miso),
		.result(mrg_bus_miso));

	lpm_mux #(
		.lpm_size(13),
		.lpm_type("LPM_MUX"),
		.lpm_width(1),
		.lpm_widths(4)) bus_busy_mux_unit (
		.sel(bus_addr[31:28]),
		.data(bus_busy),
		.result(mrg_bus_busy));

	lpm_decode #(
		.lpm_decodes(13),
		.lpm_type("LPM_DECODE"),
		.lpm_width(4)) lpm_decode_unit (
		.data(bus_addr[31:28]),
		.eq(bus_ssel));


	control control_unit (
		.clock(sys_clock),
		.rx_empty(usb_rx_empty),
		.tx_full(usb_tx_full),
		.rx_data(usb_rx_data),
		.rx_rdreq(usb_rx_rdreq),
		.tx_wrreq(usb_tx_wrreq),
		.tx_data(usb_tx_data),
		.bus_wren(bus_wren),
		.bus_addr(bus_addr),
		.bus_mosi(bus_mosi),
		.bus_miso(mrg_bus_miso),
		.bus_busy(mrg_bus_busy),
		.led(LED));

/*
	altserial_flash_loader #(
		.enable_shared_access("OFF"),
		.enhanced_mode(1),
		.intended_device_family("Cyclone III")) sfl_unit (
		.noe(1'b0),
		.asmi_access_granted(),
		.asmi_access_request(),
		.data0out(),
		.dclkin(),
		.scein(),
		.sdoin());
*/

endmodule