source: sandbox/MultiChannelUSB/Paella.v@ 167

Last change on this file since 167 was 154, checked in by demin, 14 years ago

add configuration registers for the clip module
File size: 10.2 KB
Line 
1module Paella
2 (
3 input wire CLK_100MHz,
4 output wire LED,
5
6 input wire ADC_DCO,
7 input wire ADC_FCO,
8 input wire [5:0] ADC_D,
9
10 output wire [3:0] PWM,
11
12 output wire [1:0] SPI_SEL,
13 output wire SPI_SDO,
14 output wire SPI_CLK,
15 output wire ADC_RST,
16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 output wire USB_PA2,
23 output wire USB_PA4,
24 output wire USB_PA6,
25 inout wire [7:0] USB_PB,
26
27 output wire RAM_CLK,
28 output wire RAM_WE,
29 output wire [21:0] RAM_ADDR,
30 inout wire RAM_DQAP,
31 inout wire [7:0] RAM_DQA,
32 inout wire RAM_DQBP,
33 inout wire [7:0] RAM_DQB
34 );
35
36 localparam N = 12;
37
38 // Turn output ports off
39/*
40 assign RAM_CLK = 1'b0;
41 assign RAM_CE1 = 1'b0;
42 assign RAM_WE = 1'b0;
43 assign RAM_ADDR = 20'h00000;
44*/
45 assign ADC_RST = 1'b0;
46
47 assign RAM_CLK = sys_clock;
48
49 assign USB_PA2 = ~usb_rden;
50 assign USB_PA4 = usb_addr;
51 assign USB_PA6 = ~usb_pktend;
52
53 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
54 wire usb_tx_wrreq, usb_rx_rdreq;
55 wire usb_tx_full, usb_rx_empty;
56 wire [7:0] usb_tx_data, usb_rx_data;
57 wire usb_addr;
58
59 assign USB_SLRD = ~usb_rdreq;
60 assign USB_SLWR = ~usb_wrreq;
61
62 usb_fifo usb_unit
63 (
64 .usb_clock(USB_IFCLK),
65 .usb_data(USB_PB),
66 .usb_full(~USB_FLAGB),
67 .usb_empty(~USB_FLAGA),
68 .usb_wrreq(usb_wrreq),
69 .usb_rdreq(usb_rdreq),
70 .usb_rden(usb_rden),
71 .usb_pktend(usb_pktend),
72 .usb_addr(usb_addr),
73
74 .clock(sys_clock),
75
76 .tx_full(usb_tx_full),
77 .tx_wrreq(usb_tx_wrreq),
78 .tx_data(usb_tx_data),
79
80 .rx_empty(usb_rx_empty),
81 .rx_rdreq(usb_rx_rdreq),
82 .rx_q(usb_rx_data)
83 );
84
85 wire [11:0] osc_mux_data [4:0];
86
87 wire [11:0] trg_mux_data;
88 wire trg_flag;
89
90 wire [2:0] coi_data;
91 wire coi_flag;
92
93 wire [4*12-1:0] int_mux_data [N-1:0];
94
95 wire amp_flag [N-1:0];
96 wire [11:0] amp_data [N-1:0];
97
98 wire cnt_good [N-1:0];
99 wire [15:0] cnt_bits_wire;
100
101 wire sys_clock, sys_frame;
102
103 wire [11:0] adc_data [N-1:0];
104 wire [11:0] sys_data [N-1:0];
105 wire [11:0] tst_data;
106
107 wire [11:0] cmp_data;
108 wire [11:0] del_data;
109
110 wire [20:0] cic_data [N-1:0];
111
112 wire [11:0] dec_data [N-1:0];
113 wire [11:0] clp_data [N-1:0];
114 wire [11:0] tmp_data [1:0];
115
116 wire i2c_reset;
117/*
118 sys_pll sys_pll_unit(
119 .inclk0(CLK_100MHz),
120 .c0(sys_clock),
121 .c1(ADC_DCO),
122 .c2(ADC_FCO));
123
124 wire ADC_DCO, ADC_FCO;
125
126 test test_unit(
127 .clock(ADC_FCO),
128 .data(tst_data));
129
130 adc_lvds #(
131 .size(3),
132 .width(12)) adc_lvds_unit (
133 .clock(sys_clock),
134 .lvds_dco(ADC_DCO),
135 .lvds_fco(ADC_FCO),
136 .lvds_d(36'd0),
137 .test(tst_data),
138 .trig(12'd0),
139 .adc_frame(sys_frame),
140 .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
141*/
142 sys_pll sys_pll_unit(
143 .inclk0(CLK_100MHz),
144 .c0(sys_clock));
145
146 adc_lvds #(
147 .size(6),
148 .width(24)) adc_lvds_unit (
149 .clock(sys_clock),
150 .lvds_dco(ADC_DCO),
151 .lvds_fco(ADC_FCO),
152 .lvds_d({ADC_D[5], ADC_D[4], ADC_D[3], ADC_D[2], ADC_D[1], ADC_D[0]}),
153 .adc_frame(sys_frame),
154 .adc_data({
155 adc_data[11], adc_data[10], adc_data[9], adc_data[8],
156 adc_data[7], adc_data[6], adc_data[5], adc_data[4],
157 adc_data[3], adc_data[2], adc_data[1], adc_data[0]}));
158
159 wire [15:0] cfg_bits [63:0];
160 wire [1023:0] int_cfg_bits;
161
162 wire [39:0] cfg_mux_selector;
163
164 wire cfg_reset;
165
166 wire [12:0] bus_ssel;
167 wire bus_wren;
168 wire [31:0] bus_addr;
169 wire [15:0] bus_mosi;
170 wire [15:0] bus_miso [10:0];
171 wire [12:0] bus_busy;
172
173 wire [15:0] mrg_bus_miso;
174 wire mrg_bus_busy;
175
176 wire [12*16-1:0] int_bus_miso;
177
178 genvar j;
179
180 generate
181 for (j = 0; j < 64; j = j + 1)
182 begin : CONFIGURATION_OUTPUT
183 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
184 end
185 endgenerate
186
187 configuration configuration_unit (
188 .clock(sys_clock),
189 .reset(cfg_reset),
190 .bus_ssel(bus_ssel[0]),
191 .bus_wren(bus_wren),
192 .bus_addr(bus_addr[5:0]),
193 .bus_mosi(bus_mosi),
194 .bus_miso(bus_miso[0]),
195 .bus_busy(bus_busy[0]),
196 .cfg_bits(int_cfg_bits));
197
198 generate
199 for (j = 0; j < 12; j = j + 1)
200 begin : MUX_DATA
201 assign int_mux_data[j] = {
202 amp_data[j],
203 clp_data[j],
204 cic_data[j][19:8],
205 sys_data[j]};
206 end
207 endgenerate
208
209 assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
210
211 lpm_mux #(
212 .lpm_size(4*12),
213 .lpm_type("LPM_MUX"),
214 .lpm_width(12),
215 .lpm_widths(6)) trg_mux_unit (
216 .sel(cfg_bits[4][13:8]),
217 .data({
218 int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
219 int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
220 int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
221 .result(trg_mux_data));
222
223 generate
224 for (j = 0; j < 5; j = j + 1)
225 begin : OSC_CHAIN
226
227 lpm_mux #(
228 .lpm_size(4*12),
229 .lpm_type("LPM_MUX"),
230 .lpm_width(12),
231 .lpm_widths(6)) osc_mux_unit (
232 .sel(cfg_mux_selector[j*8+5:j*8]),
233 .data({
234 int_mux_data[11], int_mux_data[10], int_mux_data[9], int_mux_data[8],
235 int_mux_data[7], int_mux_data[6], int_mux_data[5], int_mux_data[4],
236 int_mux_data[3], int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
237 .result(osc_mux_data[j]));
238 end
239 endgenerate
240
241 trigger trigger_unit (
242 .clock(sys_clock),
243 .frame(sys_frame),
244 .reset(cfg_bits[0][0]),
245 .cfg_data(cfg_bits[5][11:0]),
246 .trg_data(trg_mux_data),
247 .trg_flag(trg_flag));
248
249 oscilloscope oscilloscope_unit (
250 .clock(sys_clock),
251 .frame(sys_frame),
252 .reset(cfg_bits[0][1]),
253 .cfg_data(cfg_bits[5][12]),
254 .trg_flag(trg_flag),
255 .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
256 .ram_wren(RAM_WE),
257 .ram_addr(RAM_ADDR),
258 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
259 .bus_ssel(bus_ssel[1]),
260 .bus_wren(bus_wren),
261 .bus_addr(bus_addr[19:0]),
262 .bus_mosi(bus_mosi),
263 .bus_miso(bus_miso[1]),
264 .bus_busy(bus_busy[1]));
265
266 new_filter #(.size(12), .width(12)) filter_unit (
267 .clock(sys_clock),
268 .frame(sys_frame),
269 .reset(1'b0),
270 .inp_data({
271 sys_data[11], sys_data[10], sys_data[9], sys_data[08],
272 sys_data[7], sys_data[6], sys_data[5], sys_data[4],
273 sys_data[3], sys_data[2], sys_data[1], sys_data[0]}),
274 .out_data({
275 cic_data[11], cic_data[10], cic_data[9], cic_data[8],
276 cic_data[7], cic_data[6], cic_data[5], cic_data[4],
277 cic_data[3], cic_data[2], cic_data[1], cic_data[0]}));
278
279 generate
280 for (j = 0; j < 3; j = j + 1)
281 begin : DECONV_CHAIN
282
283 clip #(.shift(22), .width(20), .widthr(12)) clip_unit (
284 .clock(sys_clock),
285 .frame(sys_frame),
286 .reset(1'b0),
287// .del_data({6'd14, 6'd14, 6'd14, 6'd14}),
288 .del_data({cfg_bits[39+8*j][5:0], cfg_bits[37+8*j][5:0], cfg_bits[35+8*j][5:0], cfg_bits[33+8*j][5:0]}),
289 .amp_data({6'd17, 6'd17, 6'd17, 6'd17}),
290// .tau_data({16'd17193, 16'd17193, 16'd17193, 16'd17193}), /* exp(-14/1125)*1024*17 */
291 .tau_data({cfg_bits[38+8*j], cfg_bits[36+8*j], cfg_bits[34+8*j], cfg_bits[32+8*j]}),
292 .inp_data({
293 cic_data[j*4+3][19:0], cic_data[j*4+2][19:0],
294 cic_data[j*4+1][19:0], cic_data[j*4+0][19:0]}),
295 .out_data({
296 clp_data[j*4+3], clp_data[j*4+2],
297 clp_data[j*4+1], clp_data[j*4+0]}));
298
299 end
300 endgenerate
301
302 generate
303 for (j = 0; j < 12; j = j + 1)
304 begin : MCA_CHAIN
305
306 assign sys_data[j] = (cfg_bits[1][j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
307
308 amplitude #(.width(12)) amplitude_unit_2 (
309 .clock(sys_clock),
310 .frame(sys_frame),
311 .reset(1'b0),
312 .cfg_data({1'b0, 12'd0, 12'd5}),
313// .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
314// .inp_data(dec_data[j]),
315 .inp_data(clp_data[j]),
316 .out_flag(amp_flag[j]),
317 .out_data(amp_data[j]));
318 end
319 endgenerate
320
321 histogram32 histogram32_unit (
322 .clock(sys_clock),
323 .frame(sys_frame),
324 .reset(cfg_bits[0][5]),
325 .hst_good((amp_flag[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
326 .hst_data(amp_data[0]),
327/*
328 .hst_good((amp_flag[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
329 .hst_data(amp_data[j]),
330*/
331 .bus_ssel(bus_ssel[2]),
332 .bus_wren(bus_wren),
333 .bus_addr(bus_addr[12:0]),
334 .bus_mosi(bus_mosi),
335 .bus_miso(bus_miso[2]),
336 .bus_busy(bus_busy[2]));
337
338 counter hst_counter_unit (
339 .clock(sys_clock),
340// .frame((sys_frame) & (~ana_dead[0])),
341 .frame(sys_frame),
342 .reset(cfg_bits[0][8]),
343 .setup(cfg_bits[13][0]),
344 .count(cfg_bits[13][1]),
345 .bus_ssel(bus_ssel[5]),
346 .bus_wren(bus_wren),
347 .bus_addr(bus_addr[1:0]),
348 .bus_mosi(bus_mosi),
349 .bus_miso(bus_miso[5]),
350 .bus_busy(bus_busy[5]),
351 .cnt_good(cnt_good[0]));
352
353
354 i2c_fifo i2c_unit(
355 .clock(sys_clock),
356 .reset(i2c_reset),
357/*
358 normal connection
359 .i2c_sda(I2C_SDA),
360 .i2c_scl(I2C_SCL),
361
362 following is a cross wire connection for EPT
363*/
364 .i2c_sda(I2C_SCL),
365 .i2c_scl(I2C_SDA),
366
367 .bus_ssel(bus_ssel[11]),
368 .bus_wren(bus_wren),
369 .bus_mosi(bus_mosi),
370 .bus_busy(bus_busy[11]));
371
372 spi_fifo spi_unit(
373 .clock(sys_clock),
374 .reset(1'b0),
375 .spi_sel(SPI_SEL),
376 .spi_sdo(SPI_SDO),
377 .spi_clk(SPI_CLK),
378
379 .bus_ssel(bus_ssel[12]),
380 .bus_wren(bus_wren),
381 .bus_mosi(bus_mosi),
382 .bus_busy(bus_busy[12]));
383
384 pwm pwm_unit(
385 .clock(sys_clock),
386 .cfg_data({cfg_bits[31], cfg_bits[30], cfg_bits[29]}),
387 .out_data(PWM));
388
389 generate
390 for (j = 0; j < 11; j = j + 1)
391 begin : BUS_OUTPUT
392 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
393 end
394 endgenerate
395
396 lpm_mux #(
397 .lpm_size(12),
398 .lpm_type("LPM_MUX"),
399 .lpm_width(16),
400 .lpm_widths(4)) bus_miso_mux_unit (
401 .sel(bus_addr[31:28]),
402 .data(int_bus_miso),
403 .result(mrg_bus_miso));
404
405 lpm_mux #(
406 .lpm_size(13),
407 .lpm_type("LPM_MUX"),
408 .lpm_width(1),
409 .lpm_widths(4)) bus_busy_mux_unit (
410 .sel(bus_addr[31:28]),
411 .data(bus_busy),
412 .result(mrg_bus_busy));
413
414 lpm_decode #(
415 .lpm_decodes(13),
416 .lpm_type("LPM_DECODE"),
417 .lpm_width(4)) lpm_decode_unit (
418 .data(bus_addr[31:28]),
419 .eq(bus_ssel));
420
421
422 control control_unit (
423 .clock(sys_clock),
424 .rx_empty(usb_rx_empty),
425 .tx_full(usb_tx_full),
426 .rx_data(usb_rx_data),
427 .rx_rdreq(usb_rx_rdreq),
428 .tx_wrreq(usb_tx_wrreq),
429 .tx_data(usb_tx_data),
430 .bus_wren(bus_wren),
431 .bus_addr(bus_addr),
432 .bus_mosi(bus_mosi),
433 .bus_miso(mrg_bus_miso),
434 .bus_busy(mrg_bus_busy),
435 .led(LED));
436
437/*
438 altserial_flash_loader #(
439 .enable_shared_access("OFF"),
440 .enhanced_mode(1),
441 .intended_device_family("Cyclone III")) sfl_unit (
442 .noe(1'b0),
443 .asmi_access_granted(),
444 .asmi_access_request(),
445 .data0out(),
446 .dclkin(),
447 .scein(),
448 .sdoin());
449*/
450
451endmodule
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