source: sandbox/MultiChannelUSB/Paella.v@ 109

Last change on this file since 109 was 108, checked in by demin, 14 years ago

few minor fixes

File size: 9.5 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire I2C_SDA,
8 inout wire I2C_SCL,
9 inout wire [4:0] CON_A,
10 input wire [15:0] CON_B,
11 input wire [12:0] CON_C,
12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
17 input wire [2:0] ADC_D,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 localparam N = 3;
46
47 // Turn output ports off
48/*
49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
53*/
54 assign RAM_CLK = sys_clock;
55 assign RAM_CE1 = 1'b0;
56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
59 assign CON_A = 5'bz;
60 assign USB_PA0 = 1'bz;
61 assign USB_PA1 = 1'bz;
62 assign USB_PA3 = 1'bz;
63 assign USB_PA7 = 1'bz;
64// assign RAM_DQAP = 1'bz;
65// assign RAM_DQA = 8'bz;
66// assign RAM_DQBP = 1'bz;
67// assign RAM_DQB = 8'bz;
68
69 assign USB_PA2 = ~usb_rden;
70 assign USB_PA4 = usb_addr[0];
71 assign USB_PA5 = usb_addr[1];
72 assign USB_PA6 = ~usb_pktend;
73
74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
75 wire usb_tx_wrreq, usb_rx_rdreq;
76 wire usb_tx_full, usb_rx_empty;
77 wire [7:0] usb_tx_data, usb_rx_data;
78 wire [1:0] usb_addr;
79
80 assign USB_SLRD = ~usb_rdreq;
81 assign USB_SLWR = ~usb_wrreq;
82
83 usb_fifo usb_unit
84 (
85 .usb_clock(USB_IFCLK),
86 .usb_data(USB_PB),
87 .usb_full(~USB_FLAGB),
88 .usb_empty(~USB_FLAGA),
89 .usb_wrreq(usb_wrreq),
90 .usb_rdreq(usb_rdreq),
91 .usb_rden(usb_rden),
92 .usb_pktend(usb_pktend),
93 .usb_addr(usb_addr),
94
95 .clock(sys_clock),
96
97 .tx_full(usb_tx_full),
98 .tx_wrreq(usb_tx_wrreq),
99 .tx_data(usb_tx_data),
100
101 .rx_empty(usb_rx_empty),
102 .rx_rdreq(usb_rx_rdreq),
103 .rx_q(usb_rx_data)
104 );
105
106 wire [11:0] osc_mux_data [4:0];
107
108 wire [11:0] trg_mux_data;
109 wire trg_flag;
110
111 wire [2:0] coi_data;
112 wire coi_flag;
113
114 wire [7*12-1:0] int_mux_data [N-1:0];
115
116 wire ana_dead [N-1:0];
117 wire ana_good [N-1:0];
118 wire [11:0] ana_data [N-1:0];
119 wire [11:0] ana_base [N-1:0];
120
121 wire amp_good [N-1:0];
122 wire [11:0] amp_data [N-1:0];
123
124 wire cnt_good [N-1:0];
125 wire [15:0] cnt_bits_wire;
126
127 wire sys_clock, sys_frame;
128
129 wire [11:0] adc_data [N-1:0];
130 wire [11:0] sys_data [N-1:0];
131 wire [11:0] tst_data;
132
133 wire [11:0] cmp_data;
134 wire [11:0] del_data;
135
136 wire [31:0] uwt_d1 [N-1:0];
137 wire [31:0] uwt_a1 [N-1:0];
138 wire [31:0] uwt_d2 [N-1:0];
139 wire [31:0] uwt_a2 [N-1:0];
140 wire [31:0] uwt_d3 [N-1:0];
141 wire [31:0] uwt_a3 [N-1:0];
142
143 wire [1:0] uwt_flag1 [N-1:0];
144 wire [1:0] uwt_flag2 [N-1:0];
145 wire [1:0] uwt_flag3 [N-1:0];
146
147 wire [11:0] cic_mux_data;
148 wire [13:0] cic_lfsr;
149 wire [24:0] cic_data1 [N-1:0];
150 wire [24:0] cic_data2 [N-1:0];
151 wire [24:0] cic_data3 [N-1:0];
152
153 wire i2c_reset;
154
155 sys_pll sys_pll_unit(
156 .inclk0(CLK_50MHz),
157 .c0(sys_clock));
158
159 test test_unit(
160 .clock(ADC_FCO),
161 .data(tst_data));
162
163 adc_lvds #(
164 .size(3),
165 .width(12)) adc_lvds_unit (
166 .clock(sys_clock),
167 .lvds_dco(ADC_DCO),
168 .lvds_fco(ADC_FCO),
169 .lvds_d(ADC_D),
170 .test(tst_data),
171 .trig({CON_B[9:0], TRG[1:0]}),
172 .adc_frame(sys_frame),
173 .adc_data({cmp_data, adc_data[2], adc_data[1], adc_data[0]}));
174
175 wire [15:0] cfg_bits [31:0];
176 wire [511:0] int_cfg_bits;
177
178 wire [39:0] cfg_mux_selector;
179
180 wire cfg_reset;
181
182 wire [11:0] bus_ssel;
183 wire bus_wren;
184 wire [31:0] bus_addr;
185 wire [15:0] bus_mosi;
186 wire [15:0] bus_miso [10:0];
187 wire [11:0] bus_busy;
188
189 wire [15:0] mrg_bus_miso;
190 wire mrg_bus_busy;
191
192 wire [11*16-1:0] int_bus_miso;
193
194 genvar j;
195
196 generate
197 for (j = 0; j < 32; j = j + 1)
198 begin : CONFIGURATION_OUTPUT
199 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
200 end
201 endgenerate
202
203 configuration configuration_unit (
204 .clock(sys_clock),
205 .reset(cfg_reset),
206 .bus_ssel(bus_ssel[0]),
207 .bus_wren(bus_wren),
208 .bus_addr(bus_addr[4:0]),
209 .bus_mosi(bus_mosi),
210 .bus_miso(bus_miso[0]),
211 .bus_busy(bus_busy[0]),
212 .cfg_bits(int_cfg_bits));
213
214 generate
215 for (j = 0; j < 3; j = j + 1)
216 begin : MUX_DATA
217 assign int_mux_data[j] = {
218 {4'd0, uwt_flag3[j][1], 7'd0},
219 {4'd0, uwt_flag3[j][0], 7'd0},
220 {12'd0},
221// {4'd0, amp_good[j], 7'd0},
222 cic_data1[j][14:3],
223 cic_data2[j][18:7],
224 cic_data3[j][22:11],
225// {8'd0, cic_lfsr[3:0]},
226// {8'd0, cic_lfsr[5:2]},
227// uwt_a3[j][20:9],
228 sys_data[j]};
229 end
230 endgenerate
231
232 assign cfg_mux_selector = {cfg_bits[4][7:0], cfg_bits[3], cfg_bits[2]};
233
234 lpm_mux #(
235 .lpm_size(7*3),
236 .lpm_type("LPM_MUX"),
237 .lpm_width(12),
238 .lpm_widths(5)) trg_mux_unit (
239 .sel(cfg_bits[4][12:8]),
240 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
241 .result(trg_mux_data));
242
243 generate
244 for (j = 0; j < 5; j = j + 1)
245 begin : OSC_CHAIN
246
247 lpm_mux #(
248 .lpm_size(7*3),
249 .lpm_type("LPM_MUX"),
250 .lpm_width(12),
251 .lpm_widths(5)) osc_mux_unit (
252 .sel(cfg_mux_selector[j*8+4:j*8]),
253 .data({int_mux_data[2], int_mux_data[1], int_mux_data[0]}),
254 .result(osc_mux_data[j]));
255
256 end
257 endgenerate
258
259 trigger trigger_unit (
260 .clock(sys_clock),
261 .frame(sys_frame),
262 .reset(cfg_bits[0][0]),
263 .cfg_data(cfg_bits[5][11:0]),
264 .trg_data(trg_mux_data),
265 .trg_flag(trg_flag));
266
267 oscilloscope oscilloscope_unit (
268 .clock(sys_clock),
269 .frame(sys_frame),
270 .reset(cfg_bits[0][1]),
271 .cfg_data(cfg_bits[5][12]),
272 .trg_flag(trg_flag),
273 .osc_data({cmp_data[3:0], osc_mux_data[4], osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
274 .ram_wren(RAM_WE),
275 .ram_addr(RAM_ADDR),
276 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
277 .bus_ssel(bus_ssel[1]),
278 .bus_wren(bus_wren),
279 .bus_addr(bus_addr[19:0]),
280 .bus_mosi(bus_mosi),
281 .bus_miso(bus_miso[1]),
282 .bus_busy(bus_busy[1]));
283
284 cic_filter #(.size(3), .width(12)) cic_filter_unit (
285 .clock(sys_clock),
286 .frame(sys_frame),
287 .reset(1'b0),
288 .inp_data({sys_data[2], sys_data[1], sys_data[0]}),
289 .out_data2({cic_data2[2], cic_data2[1], cic_data2[0]}),
290 .out_data3({cic_data3[2], cic_data3[1], cic_data3[0]}),
291 .out_data({cic_data1[2], cic_data1[1], cic_data1[0]}));
292
293 generate
294 for (j = 0; j < 3; j = j + 1)
295 begin : MCA_CHAIN
296
297 assign sys_data[j] = (cfg_bits[1][4*j]) ? (adc_data[j] ^ 12'hfff) : (adc_data[j]);
298
299
300 analyser analyser_unit (
301 .clock(sys_clock),
302 .frame(sys_frame),
303 .reset(cfg_bits[0][2+j]),
304 .cfg_data({cfg_bits[7+2*j][12:0], cfg_bits[6+2*j][11:0]}),
305 .uwt_flag(uwt_flag2[j]),
306 .uwt_data(uwt_a2[j][17:6]),
307 .ana_dead(ana_dead[j]),
308 .ana_good(ana_good[j]),
309 .ana_data(ana_data[j]),
310 .ana_base(ana_base[j]));
311
312 amplitude amplitude_unit (
313 .clock(sys_clock),
314 .frame(sys_frame),
315 .reset(cfg_bits[0][2+j]),
316 .cfg_data(cfg_bits[12][11:0]),
317// .cfg_data(10'd5),
318 .uwt_flag(uwt_flag3[j]),
319 .uwt_data(uwt_a3[j][20:9]),
320 .amp_good(amp_good[j]),
321 .amp_data(amp_data[j]));
322 end
323 endgenerate
324
325 histogram32 histogram32_unit (
326 .clock(sys_clock),
327 .frame(sys_frame),
328 .reset(cfg_bits[0][5]),
329 .hst_good((ana_good[0]) & (cnt_good[0]) & (cfg_bits[13][1])),
330 .hst_data(ana_data[0]),
331/*
332 .hst_good((amp_good[j]) & (cnt_good[j]) & (cfg_bits[13][1])),
333 .hst_data(amp_data[j]),
334*/
335 .bus_ssel(bus_ssel[2]),
336 .bus_wren(bus_wren),
337 .bus_addr(bus_addr[12:0]),
338 .bus_mosi(bus_mosi),
339 .bus_miso(bus_miso[2]),
340 .bus_busy(bus_busy[2]));
341
342 counter hst_counter_unit (
343 .clock(sys_clock),
344 .frame((sys_frame) & (~ana_dead[0])),
345// .frame(sys_frame),
346 .reset(cfg_bits[0][8]),
347 .setup(cfg_bits[13][0]),
348 .count(cfg_bits[13][1]),
349 .bus_ssel(bus_ssel[5]),
350 .bus_wren(bus_wren),
351 .bus_addr(bus_addr[1:0]),
352 .bus_mosi(bus_mosi),
353 .bus_miso(bus_miso[5]),
354 .bus_busy(bus_busy[5]),
355 .cnt_good(cnt_good[0]));
356
357
358 i2c_fifo i2c_unit(
359 .clock(sys_clock),
360 .reset(i2c_reset),
361/*
362 normal connection
363 .i2c_sda(I2C_SDA),
364 .i2c_scl(I2C_SCL),
365
366 following is a cross wire connection for EPT
367*/
368 .i2c_sda(I2C_SCL),
369 .i2c_scl(I2C_SDA),
370
371 .bus_ssel(bus_ssel[11]),
372 .bus_wren(bus_wren),
373 .bus_mosi(bus_mosi),
374 .bus_busy(bus_busy[11]));
375
376 generate
377 for (j = 0; j < 11; j = j + 1)
378 begin : BUS_OUTPUT
379 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
380 end
381 endgenerate
382
383 lpm_mux #(
384 .lpm_size(11),
385 .lpm_type("LPM_MUX"),
386 .lpm_width(16),
387 .lpm_widths(4)) bus_miso_mux_unit (
388 .sel(bus_addr[31:28]),
389 .data(int_bus_miso),
390 .result(mrg_bus_miso));
391
392 lpm_mux #(
393 .lpm_size(12),
394 .lpm_type("LPM_MUX"),
395 .lpm_width(1),
396 .lpm_widths(4)) bus_busy_mux_unit (
397 .sel(bus_addr[31:28]),
398 .data(bus_busy),
399 .result(mrg_bus_busy));
400
401 lpm_decode #(
402 .lpm_decodes(12),
403 .lpm_type("LPM_DECODE"),
404 .lpm_width(4)) lpm_decode_unit (
405 .data(bus_addr[31:28]),
406 .eq(bus_ssel));
407
408
409 control control_unit (
410 .clock(sys_clock),
411 .rx_empty(usb_rx_empty),
412 .tx_full(usb_tx_full),
413 .rx_data(usb_rx_data),
414 .rx_rdreq(usb_rx_rdreq),
415 .tx_wrreq(usb_tx_wrreq),
416 .tx_data(usb_tx_data),
417 .bus_wren(bus_wren),
418 .bus_addr(bus_addr),
419 .bus_mosi(bus_mosi),
420 .bus_miso(mrg_bus_miso),
421 .bus_busy(mrg_bus_busy),
422 .led(LED));
423
424/*
425 altserial_flash_loader #(
426 .enable_shared_access("OFF"),
427 .enhanced_mode(1),
428 .intended_device_family("Cyclone III")) sfl_unit (
429 .noe(1'b0),
430 .asmi_access_granted(),
431 .asmi_access_request(),
432 .data0out(),
433 .dclkin(),
434 .scein(),
435 .sdoin());
436*/
437
438endmodule
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