Contact
Name
Paula Álvarez Rengifo
Position
Former member
PhD student in CP3 from November 2010 to June 2017
Projects
I am involved in the following research direction:

TRAPPISTe: Tracking for Particle Physics Instrumentation in SOI Technology

The TRAPPISTe series of sensors tries to use SOI technology to build a monolithic pixel sensor. SOI wafers consist of a thin top silicon active layer, a middle insulating buried oxide layer and a thick handle wafer. Due to the insulating layer, SOI technology allows for more compact layout and lower parasitics compared to traditional bulk CMOS processes.

The TRAPPISTe-1 sensor was designed and fabricated at UCL’s WINFAB facility at the Ecole Polytechnique de Louvain. WINFAB provides a 2m Fully Depleted SOI process with the following characteristics:

• 100nm top active layer, 400nm buried oxide layer, 450um handle wafer
• substrate: 15-25 Ωcm, p-type
• four types of transistors with different threshold voltages: low Vt, standard Vt, high Vt, graded.

The first fabrication of the TRAPPISTe-1 chip was delivered in January 2010. Unfortunately, the process was complicated by a contamination resulting in a voltage shift of all the transistors. A second run of the TRAPPISTe-1 chip is currently being produced.

The TRAPPISTe-2 project has just begun with the SOIPIX collaboration and will use OKI Semiconductor 0.2um technology to build a pixel sensor and test structures. The OKI technology provides the following:

• active layer thickness 50nm, BOX thickness 200nm, handle wafer thickness 250-350um
• substrate resistivity of 700 Ωcm, n-type
• 4 metal layers
• buried p-well (BPW) to suppress back gate effect

TRAPPISTe-2 chips have been delivered by OKI in the beginning of 2011. To test the TRAPPISTe chip, a readout board and a laser test station are being developed. The readout board consists of a daughter board and main board. The daughter board is a small board used for mounting and bonding the TRAPPISTe chip. Several daughter boards have been designed to accommodate the TRAPPISTe-1 and TRAPPISTe-2 chips. The daughter boards plug into the main board which contains DACs to set the appropriate bias voltages and an ADC controlled by an FPGA to read the detector output. A laser test station is being commissioned to test the charge collection of the device.

The TRAPPISTe project has been presented at the following conferences:
- iWoRiD 2009
- IEEE Nuclear Science Symposium 2009
- Vienna Conference on Instrumentation 2010

TRAPPISTe group has also joined the SOIPIX collaboration and was presented at the SOIPIX Collaboration Meeting 2010. SOIPIX is an international research collaboration developing detector applications in SOI technology. More information on the TRAPPISTe project can be found at: https://server06.fynu.ucl.ac.be/projects/cp3admin/wiki/UsersPage/Physics/Hardware/Trappiste.

External collaborators: Denis Flandre (UCLouvain - EPL) Elena Martin (Universitat Autonoma de Barcelona).


Show past projects.
Publications in CP3
All my publications on Inspire


[UCLouvain] - [SST] [IRMP] - [SC]
Contact : Jérôme de Favereau
Research
Job opportunities Post-doctoral positions in BSM phenomenology at colliders and in astrophysics
Postdoctoral Position on advanced analysis techniques applied to the CMS di-Higgs study
Post-doctoral positions in collider phenomenology and particle astrophysics
EOS be.h : 10 PhD positions