Development of simulation tools at device level for semiconductor sensors. We are interested both in the simulation of static characteristics as for instance coupling capacitances, electric fields, etc, but also dynamic characteristics as signal developed in different sensors when particles are passing through. Tools used to made this simulations are based in comercial software as TCAD or Silvaco and programs developed by ourselves. This work profits from the close collaboration with DICE (FSA/UCL).
External collaborators: Denis Flandre (UCLouvain - EPL).
Gigatracker is in the core of one of the spectrometers used in NA62. It's composed of three planes of silicon pixels detectors assembled in a traditional way: readout electronics bump bonded on silicon sensors. Each plane is composed by 18000 pixels 300 um x 300 um arranged in 45 columns and readout by 10 chips. The particularity of this sensor is that its timing resolution should be better than 200 ps in order to cope with high expected rate (800 MHz). Another particularity is its operation in vacuum. CP3 is involved in several aspects in the construction of this detector. 1) Signal development of the signal in the sensor. We use both commercial programs (i.e. TCAD by Synopsys) as well as software developed by us to study the expected signal of this sensor. This step is of high importance to design and scale properly the readout electronics readout. 2) Design and test of the readout chip. We are participation in the design of one of the two proposed chips to perform the sensor readout, the so called End-Of-Column option. We will participate also in the test both at lab as well as under beam of this chip. This work is being done in collaboration with CERN and INFN (Torino). 3) Support mechanics and cooling. CP3 is one of the responsible institutes in the design, construction and assembly of the support mechamics and cooling. The whole system should be light, able to operate in vacuum as well as assure a thermal stability. This work is done in collaboration with INFN (Ferrara) A campaign of test beams has been scheduled in order to fully qualify this detector.
LARA: LAser for Radiation Analysis LARA is a general purpose laser testbench devoted to study the radiation susceptibility of semiconductor devices. The systems consists in a high precission step motors (~0.1 um), a 1060 nm pulsed laser (PiLAS) with associated optics to obtain beam spots f ~5-6 um, and a set of photodetectors to measure both integrated and pulse-by-pulse optical power. LARA will have two main applications: 1. Test of semiconductor sensors (pixel, microstrips, etc). 2. Study of single event effects (SEE) in semiconductor components. A set of standard measurement equipment will be available to perform measurements for both type of applications.
The TRAPPISTe series of sensors tries to use SOI technology to build a monolithic pixel sensor. SOI wafers consist of a thin top silicon active layer, a middle insulating buried oxide layer and a thick handle wafer. Due to the insulating layer, SOI technology allows for more compact layout and lower parasitics compared to traditional bulk CMOS processes. The TRAPPISTe-1 sensor was designed and fabricated at UCL’s WINFAB facility at the Ecole Polytechnique de Louvain. WINFAB provides a 2m Fully Depleted SOI process with the following characteristics: • 100nm top active layer, 400nm buried oxide layer, 450um handle wafer • substrate: 15-25 Ωcm, p-type • four types of transistors with different threshold voltages: low Vt, standard Vt, high Vt, graded. The first fabrication of the TRAPPISTe-1 chip was delivered in January 2010. Unfortunately, the process was complicated by a contamination resulting in a voltage shift of all the transistors. A second run of the TRAPPISTe-1 chip is currently being produced. The TRAPPISTe-2 project has just begun with the SOIPIX collaboration and will use OKI Semiconductor 0.2um technology to build a pixel sensor and test structures. The OKI technology provides the following: • active layer thickness 50nm, BOX thickness 200nm, handle wafer thickness 250-350um • substrate resistivity of 700 Ωcm, n-type • 4 metal layers • buried p-well (BPW) to suppress back gate effect TRAPPISTe-2 chips have been delivered by OKI in the beginning of 2011. To test the TRAPPISTe chip, a readout board and a laser test station are being developed. The readout board consists of a daughter board and main board. The daughter board is a small board used for mounting and bonding the TRAPPISTe chip. Several daughter boards have been designed to accommodate the TRAPPISTe-1 and TRAPPISTe-2 chips. The daughter boards plug into the main board which contains DACs to set the appropriate bias voltages and an ADC controlled by an FPGA to read the detector output. A laser test station is being commissioned to test the charge collection of the device. The TRAPPISTe project has been presented at the following conferences: - iWoRiD 2009 - IEEE Nuclear Science Symposium 2009 - Vienna Conference on Instrumentation 2010 TRAPPISTe group has also joined the SOIPIX collaboration and was presented at the SOIPIX Collaboration Meeting 2010. SOIPIX is an international research collaboration developing detector applications in SOI technology. More information on the TRAPPISTe project can be found at: https://server06.fynu.ucl.ac.be/projects/cp3admin/wiki/UsersPage/Physics/Hardware/Trappiste.
External collaborators: Denis Flandre (UCLouvain - EPL) Elena Martin (Universitat Autonoma de Barcelona).
